I am trying to write/read the AXI VDMA's AXI Lite interface for configuring the core and monitoring its status.
However, I have verified with Vivado Logic Analyzer that valid requests are issued to the VDMA, but accesses occasionally fail.
For example, I write value 0xaaaaaaaa to a given register then I write 0x55555555 to the same register.
When I read that same register, it does not report 0x55555555 as expected.
What is the cause of this issue?
This behavior can happen if you violate the cores requirement that the AXI Lite clock must be the slowest clock in the system.
According to the Product Guide for the core:
"In asynchronous mode, the frequency of s_axi_lite_aclk <= m_axi_mm2s_aclk or m_axi_s2mm_aclk."
In order to resolve the issue, the clock topology must be fixed.