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AR# 59444

Vivado HLS 2013.4 - Example to generate PLB IP for older systems

Description

This answer record gives an Example Design of how to create and integrate PLB bus IP with the 2013.4 version of VHLS to target previous generation devices such as Spartan-3 or Spartan-6.

Please note that PLB support is removed from the Vivado HLS tool since version 2012.3 and that the last documentation describing the directives is 2012.2; this is the version used to get the correct directives.

NOTE: This Example Design is provided "as-is" and is unsupported.

An Example Design is an answer record that provides technical tips to test a specific functionality of the tools. A tip can be a snippet of code, a snapshot, a diagram, or a full design implemented with a specific version of the Xilinx tools. It is up to the user to "update" to future Xilinx tool releases and to "modify" the Example Design to fulfill the user's needs. Limited support is provided by Xilinx on these Example Designs.

Solution

Since PLB is not supported in VHLS 2013.4, there are some pitfalls or issues that need manual edits to the generated code.

The sections below show some of the issues and how they are addressed.

Vivado HLS part

The two small ZIP files (plb_master.zip and sdk_struct_as_array.zip) are the Vivado HLS source code, use vivado_hls -f run_hls.tcl to re-run from the command line and regenerate the GUI project, etc. You need to make sure the part/FPGA device matches yours; this example defaults to a Spartan-6.

In generated IP change MPD, use "others" or the part used in the XPS project:

OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)

XPS part

Copy the pcores over from VHLS into the pcore directory of the XPS project. Connect the IPs , the aclk bus clock, aresetn to the peripheral_aresetn, set the address mapping.

As PLB support has been dropped, the PLB master wrapper generated is wrong and edits are needed to remove the unconnected inputs if_read_ce and if_write_ce in the fifo code.

You need to comment out the references to inputs if_read_ce and if_write_ce in the fifo code.

The ZIP (XPS_S6LX9MB.zip) shows the MHS file used and the XPS project.

SDK part

sdk_plb_master.zip and sdk_struct_as_array.zip are two SDK application projects.

The SDK application only needs the header file for the register mapping and the main functions.

Since no APIs are generated by the VHLS tool, direct access to the IP are generated.

The user is free to implement his own API, in a similar way to what is generated for supported AXI bus.

As the xil_printf function do not support floating points to keep the code size small a function that display the floating point as a fraction was used: you can verify that the same output result is computed from the C simulation testbench created from the first part.

Attachments

Associated Attachments

Name File Size File Type
plb_master.zip 10 KB ZIP
struct_as_arrays.zip 5 KB ZIP
XPS_S6LX9MB.zip 2 KB ZIP
sdk_plb_master.zip 1 KB ZIP
sdk_struct_as_array.zip 1 KB ZIP
AR# 59444
Date Created 02/17/2014
Last Updated 02/18/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite
  • EDK - 14.7