We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59457

Failed to get a response from the Debug Core Hub


The Zynq processing system FCLK(x) does not run unless some registers in the Processing System (PS) are modified. 

This means that the design in the Programming Layer (PL) will not operate until this is done. 

This will affect any connection to the PL design with Debug Cores/ ILA/VIA/JTAG. 

As soon as the hardware is programmed the following error might appear:

ERROR: [Labtools 27-1437] Failed to get a response from the Debug Core Hub on device XC7Z020_1 (JTAG device index = 1), in user chain = 1.


1) Verify that the clock signal connected to the debug core is clean and free-running.

2) Verify that the clock connected to the debug core meets all timing constraints.

It is important to use SDK to program the Zynq PL when the dbg_hub cores XSDB_CLK clock input is connected to the PS7s FCLK_CLK0 output.

AR# 59457
Date Created 02/18/2014
Last Updated 04/28/2014
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2013.3
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit