We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59502

2013.3 Vivado IP Flows - Generating user packaged IP gives [IP_​Flow 19-152] Failed to convert bitString value '0x12345678' to HDL value.


In my top-level VHDL file I have two generics:
       my_std_logic_vector: STD_LOGIC_VECTOR (3 downto 0) := "1111";
       my_unsigned:         UNSIGNED (3 downto 0) := "1010");

It looks like the both of the generics are successfully processed by the IP Packager.

When the packaged IP is imported into the IP Catalog of the final design, the IP GUI represents information in a correct way.
However, when I click OK to generate the IP I receive an error from Vivado saying that it is not possible to generate the IP:

ERROR: [Common 17-39] generate_target failed due to earlier errors.

In the message window there are several messages similar to the following:
    [IP_Flow 19-152] Failed to convert bitString value '"1010"' to HDL value.

In the generated wrapper ( my_adder_0.vhd ) there is no value for my_unsigned in the generic map.

  U0 : my_adder
      width => 8,
      rst_enable => true,
      my_std_logic_vector => B"1111",
      my_unsigned => 
This issue is seen with both UNSIGNED and SIGNED generics.


This issue arises in Vivado 2013.3.

It has been fixed in Vivado 2013.4
AR# 59502
Date 08/26/2014
Status Archive
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite - 2013.3
Page Bookmarked