UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59515

MIG 7 Series - Vivado does not generate the correct VHDL instantiation template

Description

Version Found: MIG 7 Series v2.0 Rev 2
Version Resolved: See (Xilinx Answer 54025)

The MIG 7 Series VHDL instantiation template file (.VHO) is not generated correctly. 

The syntax is not correct and is missing the component declaration.

Solution

To work around the issue, open the example design and view the instantiation of the MIG core in the example design for reference.

Revision History
03/04/2014 - Initial release

AR# 59515
Date Created 02/24/2014
Last Updated 04/15/2014
Status Active
Type Known Issues
Devices
  • Virtex-7
  • Kintex-7
Tools
  • Vivado Design Suite - 2013.4
IP
  • MIG 7 Series