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AR# 59532

Vivado High level Synthesis (HLS) AXI DMA example design with Ping-Pong Buffer

Description

Attached is the C++ design for a HLS AXI DMA (configurable for either GP or HP Zynq interfaces). 


Solution

The design creates a ping pong buffer (via #pragma HLS DATAFLOW) of user defined length & width.  

A C++ test bench is included. 

The advantages are reduced size (compared to AXI Datamover, AXI VDMA) and simplification (no software programming is required to start using).  

Another advantage is a user configurable processor interrupt that notifies the Cortex A9 after x words of data have been transferred (to allow the processor to start processing the data while data is still being moved).

Attachments

Associated Attachments

Name File Size File Type
stream2pingPong.cpp 7 KB CPP
stream2pingPong.h 140 Bytes H
tb_stream2pingPong.cpp 4 KB CPP
AR# 59532
Date Created 02/25/2014
Last Updated 03/11/2015
Status Active
Type General Article
Tools
  • AutoESL