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AR# 59555

LogiCORE IP S/PDIF - Where can I find the XDC constraints for this IP?

Description

Where can I find the XDC constraints for this IP?

In 2013.4 and earlier the S/PDIF core sometimes produces timing errors with the provided XDC constraints.


Where can I find the proper constraints for the S/PDIF Core?

Solution

The constraints are updated in Vivado 2014.1.

For users in prior releases, an updated set of constraints for the LogiCORE S/PDIF core can be found below:

7-Series RX Mode:
set_false_path -from [get_pins -hierarchical -filter {NAME =~ inst/spdif_inst/AXI_REGISTER_IF_I/SOFT_RESET_I/RESET_FLOPS*/*}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ inst/spdif_inst/AXI_REGISTER_IF_I/SPDIF_REG_MODULE_I/*/*}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ inst/spdif_inst/AXI_REGISTER_IF_I/SPDIF_REG_MODULE_I/spdif_control_reg_reg*/*}]
set wr_clock [get_clocks -of_objects [get_ports aud_clk_i]]
set rd_clock [get_clocks -of_objects [get_ports m_axis_aclk]]
set_max_delay -from [get_cells -hierarchical -filter {NAME =~ *ASYNC_RX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~ *ASYNC_RX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property PERIOD $wr_clock]
set_max_delay -from [get_cells -hierarchical -filter {NAME =~ *ASYNC_RX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~ *ASYNC_RX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property PERIOD $rd_clock]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ *ASYNC_RX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.*/g*as.*sts/ram_*_i_reg/*}]
set_false_path -to [get_pins -hier *cdc_to*/D]
 
7-Series TX Mode:
set_false_path -from [get_pins -hierarchical -filter {NAME =~ inst/spdif_inst/AXI_REGISTER_IF_I/SOFT_RESET_I/RESET_FLOPS*/*}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ inst/spdif_inst/AXI_REGISTER_IF_I/SPDIF_REG_MODULE_I/*/*}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ inst/spdif_inst/AXI_REGISTER_IF_I/SPDIF_REG_MODULE_I/spdif_control_reg_reg*/*}]
set wr_clock [get_clocks -of_objects [get_ports s_axis_aclk]]
set rd_clock [get_clocks -of_objects [get_ports aud_clk_i]]
set_max_delay -from [get_cells -hierarchical -filter {NAME =~ *ASYNC_TX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~ *ASYNC_TX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property PERIOD $rd_clock]
set_max_delay -from [get_cells -hierarchical -filter {NAME =~ *ASYNC_TX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~ *ASYNC_TX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property PERIOD $wr_clock]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ *ASYNC_TX_FIFO_I*/*inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.*/g*as.*sts/ram_*_i_reg/*}]
set_false_path -to [get_pins -hier *cdc_to*/D]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54543 LogiCORE IP S/PDIF - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 59555
Date Created 02/26/2014
Last Updated 05/28/2014
Status Active
Type General Article
IP
  • SPDIF