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AR# 59562

14.X Place -ERROR:Place:1177 - Unroutable Placement! A BUFGMUX that drives a PLL on the DCLK pin is not placed at a routable site

Description

When I implement a design containing DRP PLL in Spartan-6, I receive the following error message:

ERROR:Place:1177 - Unroutable Placement! A BUFGMUX that drives a PLL on the DCLK

   pin is not placed at a routable site. The BUFGMUX component <BUFG_IN> is

   placed at site <BUFGMUX_X2Y9>. The PLL component <PLL_ADV_inst> is placed at

   <PLL_ADV_X0Y3>. The BUFGMUX can drive the PLL.DCLK pin if the BUFGMUX is in

   TOP half of the chip. This placement is UNROUTABLE in PAR and therefore, this

   error condition should be fixed in your design. You may use the

   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a

   WARNING in order to generate an NCD file. This NCD file can then be used in

   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this

   clock placement rule is listed below. These examples can be used directly in

   the .ucf file to demote this ERROR to a WARNING.

   < PIN "BUFG_IN.O" CLOCK_DEDICATED_ROUTE = FALSE; >

   < PIN "PLL_ADV_inst.DCLK" CLOCK_DEDICATED_ROUTE = FALSE; >

How can I solve this issue?

Solution

As per the advice in the error message, only use BUFGMUX in the top half of the chip to drive the DCLK pin of the PLL.

Available BUFGMUX: BUFGMUX_X2Y1~ BUFGMUX_X2Y4, BUFGMUX_X3Y5~ BUFGMUX_X3Y8.

 


AR# 59562
Date Created 02/27/2014
Last Updated 03/25/2015
Status Active
Type General Article
Tools
  • ISE Design Suite - 14