We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59583

2013.4 - Vivado crashes when running set_property HD.PARTPIN_RANGE


Vivado crashes when running the following command:

set_property HD.PARTPIN_RANGE $range [get_pins -of_objects [get_cells -of_objects [get_pblocks $pblock]]]


This crash does not occur in Vivado 2014.1.

In Vivado 2014.1, a warning message appears instead:

set_property HD.PARTPIN_RANGE $range [get_pins -of_objects [get_cells -of_objects [get_pblocks $pblock]]]

WARNING: [Vivado 12-2268] Pin miami_i/dyplo_axi_0/U0/pr_nodes_gen.dyplo_pr_nodes[0].dyplo_pr_node_i/dyplo_hdl_node_i/dab_addr[0] is not connected to any net, will not set PartPin Range.
WARNING: [Vivado 12-2268] Pin miami_i/dyplo_axi_0/U0/pr_nodes_gen.dyplo_pr_nodes[0].dyplo_pr_node_i/dyplo_hdl_node_i/dab_addr[1] is not connected to any net, will not set PartPin Range.
WARNING: [Vivado 12-2259] HD.PARTPIN_RANGE can only be set on non-clock pin: miami_i/dyplo_axi_0/U0/pr_nodes_gen.dyplo_pr_nodes[0].dyplo_pr_node_i/dyplo_hdl_node_i/dab_clk is a clock pin.

The HD.PARTPIN_RANGE constraint is only valid for pins or ports that do not have dedicated connections (for example, clocks or direct connections to top-level I/O pads).

The constraint will be ignored if it is applied. 

AR# 59583
Date Created 02/28/2014
Last Updated 12/10/2014
Status Active
Type General Article
  • Zynq-7000