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AR# 59598

Vivado Simulator FAQ - How do I simulate with a single language simulator?


I have a Verilog only licensed simulator.
How can I ensure that I can simulate Xilinx designs using it?
How do I simulate designs with a single language simulator?


Most Xilinx IP deliver behavioral simulation models for a single language only, effectively disabling simulation for language-locked simulators if you are not licensed for the appropriate language.
The simulator_language property ensures that an IP delivers a simulation model for any given language. 
Vivado Design Suite ensures the availability of a simulation model by using the available synthesis files of an IP to generate a language-specific structural simulation model on demand.
For cases in which a behavioral model is missing or does not match the licensed simulation language, the Vivado tools automatically generate a structural simulation model to enable simulation.
Otherwise, the existing behavioral simulation model for the IP will be used. 

The table below illustrates the function of the simulator_language property.
To know what models are delivered by the IP, kindly refer to the IP Data Sheet.
You can set simulator_language while creating your project in Vivado and also under Project Options > Simulation as displayed below:

New Project Window


Project Settings > Simulation


For TCL it can be set as a property. For example:
set_property simulator_language VHDL [current_project]
  1. If no synthesis or simulation files exist, simulation is not supported.
  2. Where available, Behavioral Simulation will always take precedence and be advertised over Structural Simulation.
    You will not be offered a choice of simulation mode.
  3. The simulator_language property will not be able to deliver netlist simulation files if the Generated Synthesized Checkpoint (.dcp) option is unchecked when generating IP output products 
AR# 59598
Date 07/31/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.4
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