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AR# 59624

MIG 7 Series - Can the input system clock (sys_clk) be driven by the IBUFDS_GTE2?


In order to reduce the number of oscillators required is it possible to drive the MIG sys_clk from an IBUFDS_GTE2?


This is not possible as the sys_clk must be routed on the CLOCK_DEDICATED_ROUTE BACKBONE and the IBUFDS_GTE2 does not have access to this. 

The tools will not generate a DRC error, however it is not a supported clocking topology.

Revision History

08/14/14 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40603 MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines N/A N/A
AR# 59624
Date Created 03/04/2014
Last Updated 08/15/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series