UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59647

Zynq-7000 AP SoC - SPI - A glitch is observed on the MOSI line immediately following the assertion of Slave Select signal or at byte boundary

Description

While operating the PS7 SPI block in master mode, a glitch is observed on the MOSI line immediately following the assertion of a Slave Select signal or at byte boundary.

 

Solution

The duration of the glitch is one ref_clk cycle but it is not eating into hold/setup time on the previous/next sample point.
 
Impact:                     None.
 
Work-around:           The user can safely ignore the glitch as it does not impact the functionality.
 
Configurations          All Zynq devices when SPI in master mode, CPHA and CPOL are set to 00 or 11.
Affected:
 
Resolution:               Not Fixed                                                                                       
AR# 59647
Date Created 03/05/2014
Last Updated 05/05/2015
Status Active
Type General Article
Devices
  • Zynq-7000