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AR# 59742

Viviado Implementation - Incremental flow causes "Error: [Drc 23-20] Rule violation (UCIO-1)"


When using the incremental flow of Implementation (a placed DCP is used as a guide file), DRC errors similar to the following are received when generating the bitstream:

Error: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 6 out of xxx logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: xxxxxx.

These ports do have package_pin constraints in XDC and their placement matches the constraints.

There are no critical warnings about the 6 package_pin constraints.

The .xdc file exported by write_xdc in the implemented design contains these 6 constraints.

What is the problem?


If the reported ports have the correct package_pin constraints in XDC, then these are incorrect DRC errors.

To work around this issue, use the Tcl command suggested in the error message to downgrade the DRC error to a warning.

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

This command can also be put in a .tcl file which can then be set in the tcl.pre option of the Write Bitstream settings in the Implementation settings.
AR# 59742
Date Created 03/11/2014
Last Updated 03/23/2015
Status Active
Type General Article
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2014.1