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AR# 59781

Vivado IPI PS7-only design fails with GLOBAL_LOGIC0 as UNROUTED net during route_design due to synthesis issues

Description

I have created a simple IPI PS7-only design in Vivado 2013.4.

The final result shows 1 failed route.

The Route Status Report states the following:
 



Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 2125 :
# of nets not needing routing.......... : 1086 :
# of internally routed nets........ : 450 :
# of nets with no loads............ : 636 :
# of routable nets..................... : 1039 :
# of fully routed nets............. : 1038 :
# of nets with routing errors.......... : 1 :
# of nets with some unrouted pins.. : 1 :
------------------------------------------- : ----------- :


Nets with Routing Errors:
GLOBAL_LOGIC0
Unrouted Pins -- only the first 10 are listed, use -show_all to get the full list:
design_1_i/processing_system7_0/inst/PS7_i/DDRDM[2]
design_1_i/processing_system7_0/inst/PS7_i/DDRDM[3]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQSN[2]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQSN[3]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQSP[2]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQSP[3]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQ[16]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQ[17]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQ[18]
design_1_i/processing_system7_0/inst/PS7_i/DDRDQ[19]

Solution

Root Cause:
 
The lower level primitive (PS7) has pins tied to upper levels, but then levels above the pins are unconnected.
 
Instead of leaving the pins of the primitive unconnected, the tool ties off the upper level to 0, and then does constant prop all the way down to the primitive. 

Workaround:
 
Use the parameter below in the Tcl console before running Synthesis and Implementation in Vivado 2013.4.
 

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter retainUnconnectedPinsForPrimBBox true"


This parameter tells the tool to retain the Unconnected pins for Xilinx Primitives and Black Boxes, and not to connect it to 0.
AR# 59781
Date Created 03/13/2014
Last Updated 04/09/2015
Status Active
Type Error Message
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
  • More
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Less