I instantiate a BRAM primitive (Such as RAMB18E1, RAMB36E1) or BRAM Macro (Such as BRAM_TDP_MACRO, BRAM_SDP_MACRO) in my design, and set the INIT_FILE attribute in the Verilog / VHDL code.
However, the content of the initial file is not loaded into the BRAM.
Is this expected behavior?
This is an expected behavior.
Vivado Synthesis uses the contents of the INIT_FILE during RAM inference, not instantiation.
In case of instantiation of the RAM primitives directly by the user, synthesis will just pass on the instantiated primitive to the generated netlist in which case the INIT_FILE name is also passed on with the netlist.
Synthesis does not load the INIT_FILE values here since there is no inference.
The tool has not been told to load the values via an external file or via one of the above mentioned procedures for VHDL & Verilog.
The underlying BRAM will have the default value of 0's for these cases on INIT_XX.