We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59808

2013.4 Sysgen - connect_bd_net errors in IP Catalog flow


I am running Lab 9 from (UG948) and when I attempt to compile the gain_control.slx design, the following errors occur:

WARNING: [BD 5-235] No pins matched 'get_bd_pins /proc_sys_reset_1/ext_reset_in'
ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net
ERROR: [BD 5-4] Error: running connect_bd_net.
ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.
ERROR: An error occurred when creating the Vivado project.

Is this a known issue?


This is a known issue discovered in Vivado Design Suite 2013.4 and fixed in the 2014.1 release.

As a workaround, please use 2013.3 which also does not exhibit this error behavior.

Note: the IP is correctly generated in 2013.4,t is just the example MicroBlaze project that is not automatically created. 

Therefore, you can still use the Sysgen generated AXI IP in 2013.4.

AR# 59808
Date Created 03/17/2014
Last Updated 02/18/2015
Status Active
Type General Article
  • Vivado Design Suite
  • Vivado Design Suite - 2013.4