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AR# 59837

2013.4 data2mem - ERROR:Data2MEM:26 - Illegal bit lane width in ADDRESS_SPACE

Description

I created 256 Byte (8 bit x 256 word) BRAM with Block Memory Generator.

RAMB18 is used for the BRAM.

I am trying to use data2mem with the following BMM file to initialize the BRAM data.

ADDRESS_SPACE initrom RAMB18 [0x0000:0x00FF]
  BUS_BLOCK
    bmg0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.WIDE_PRIM18.ram [7:0] PLACED = X0Y76;
  END_BUS_BLOCK;
END_ADDRESS_SPACE;

I am receiving the error below.

ERROR:Data2MEM:26 - Illegal bit lane width in ADDRESS_SPACE 'initrom'.
    'bmg0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.WIDE_PRIM18.ram [7:0]' is 8 bits wide. Only 1, 2, 4, 9, 18, 36 bit widths are allowed for this device.


How can I solve this error?

Solution

"RAMB18" should be specified in BMM only when BRAM is used with parity.

If you are not using the parity in BRAM, you should specify "RAMB16" instead of "RAMB18" in BMM.
 
Although you are using only 256 Byte in RAMB18, one "RAMB16" contains 2K Byte.

You need to change the address space to [0x0000:0x07FF] from [0x0000:0x00FF].

ADDRESS_SPACE initrom RAMB16 [0x0000:0x07FF]
  BUS_BLOCK
    bmg0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/NO_BMM_INFO.SP.WIDE_PRIM18.ram [7:0] PLACED = X0Y76;
  END_BUS_BLOCK;
END_ADDRESS_SPACE;
AR# 59837
Date Created 03/18/2014
Last Updated 03/26/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite