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AR# 59933

2013.4 Vivado synthesis generates incorrect logic on the address line of the inferred BRAM


Vivado Synthesis generates incorrect logic when moving a register across concat to be near a RAM for BRAM inference.

Here is sample code that reflects this issue:
Rdaddr = {2b11, rd_reg[4:0]}


For the above mentioned sample code, a concat node is created within the tool's internal data structure.

In this case, and for the sake of improved timing, the Vivado synthesis tool moved the register across this concat node and nearer to the RAM for BRAM inference.

In this process, due to the presence of the 2 bit constants, there was an issue with initial value computation when rd_reg was reset after the register move over concat.

This happens only on the read address line, and is specific to inferred BRAM.

This issue has been fixed in 2014.1.

To work around it in 2013.4, use the KEEP property on the register signals, this prevents these registers from being moved.

(*keep = "true" *)  reg [5:0] rd_reg;

AR# 59933
Date 04/17/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.4
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