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AR# 59944

Vivado Timing - Vivado and ISE give different Total System Jitter (TSJ) on the same input or output path


For the same input or output path, Vivado and ISE give different Total System Jitter (TSJ) values.

What causes the discrepancy?


ISE and Vivado calculate the Total System Jitter on input and output paths differently.

Vivado analyzes all paths as a register to register path type.

It assumes we have a register outside of the FPGA for the input paths and output paths.

So it calculates as TSJ = (SJ2 + SJ2)1/2 to take both source and destination into account.

This matches the industry standard static timing analysis tools.

ISE analyzes the input and output paths only on the FPGA side.

It only counts the destination for input paths and the source for output paths for Total System Jitter: TSJ = (SJ2)1/2 = SJ.

This is why the TSJ from Vivado is higher than that of ISE and this results in the ISE slack being a bit higher than the Vivado slack on input and output paths.

When virtual clock is used in the set_input_delay/set_output_delay constraints, Vivado only counts for the FPGA side and gives the same Total System Jitter as ISE Timing Analyzer.

For more details of Total System Jitter, please refer to (Xilinx Answer 37702).
AR# 59944
Date 08/05/2014
Status Active
Type General Article
  • Vivado Design Suite
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