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AR# 59986

2014.1 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2014.1 in a single location which allows you to see all IP changes without having to installing the Vivado Design Suite.

Solution

c) Copyright 2014 Xilinx, Inc. All rights reserved.

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100G Ethernet (1.1)

 * Version 1.1

 * GTH Implementation on XCVU095-FFVD1924 device only without bitstream support. This is due to the timing information not being accurate; designs may fail timing

 * GTY simulation only support for CAUI-10, CAUI-4, and Switchable Mode CAUI-10/CAUI-4

 * Synchronous / Asynchronous Clocking Mode

 * Shared Logic in core / example design

 * XSIM / Questa (10.2a) / VCS (H-2013.06-sp1) / IES (12-20.016)

32-bit Initiator/Target for PCI (7 Series) (5.0)

 * Version 5.0 (Rev. 4)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enabled third party synthesis tools to read encrypted netlists (but not source HDL)

 * Added support for 35t,50t and 75t Artix7 devices

3GPP LTE Channel Estimator (2.0)

 * Version 2.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

 * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral simulation and post- netlists. VCS version I-2014.03-Beta1 or later is recommended.

3GPP LTE MIMO Decoder (3.0)

 * Version 3.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

3GPP LTE MIMO Encoder (4.0)

 * Version 4.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * All event output signals of this core are unimplemented and will be constant '0'.

 * Support for Virtex UltraScale devices at Pre-Production Status

3GPP Mixed Mode Turbo Decoder (2.0)

 * Version 2.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

3GPP Turbo Encoder (5.0)

 * Version 5.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Added default value to internal signal to ensure behavioral simulation is consistent with post-synthesis functional simulation. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

3GPPLTE Turbo Encoder (4.0)

 * Version 4.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

64-bit Initiator/Target for PCI (7 Series) (5.0)

 * Version 5.0 (Rev. 4)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enabled third party synthesis tools to read encrypted netlists (but not source HDL)

 * Added support for 35t,50t and 75t Artix7 devices

7 Series FPGAs Transceivers Wizard (3.2)

 * Version 3.2

 * Added support for Aartix35T, Aartix50T, Aartix75T

 * Fixed simulation issue for GTX Buffer bypass AUTO mode

 * Added support for XC7VH870T and XC7VH580T FLG package devices

7 Series Integrated Block for PCI Express (3.0)

 * Version 3.0 (Rev. 1)

 * Added Zynq7015 device support

 * Added 35t,50t and 75t support for Artix7l and Aartix7 devices

 * Added cpg236 and csg325 packages support for Artix7 devices

 * Enabled Tandem PROM configuration support for Zynq 7030 and for Zynq7045 devices

 * Enabled Tandem Configuration support for Kintex 420T device

 * Changed the directory structure of the core without affecting the design hierarchy

AHB-Lite to AXI Bridge (3.0)

 * Version 3.0

 * Removed output ports m_axi_aclk and m_axi_aresetn

 * Added GUI option to support secured access on AXI-Lite interface

 * Enhanced Support for IP Integrator

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI 10G-Ethernet (1.2)

 * Version 1.2

 * Added optional support for an alternative 1588 timer format.  This is a 64-bit fractional nanoseconds field, similar to the 1588 correction Field definition, which enables the ability to provide 1-step support for all device types (including transparent clocks).

 * Fixed issues in the transmitter UPD checksum update logic

 * Fixed issues in the transmitter 1-step timestamp insertion logic

 * Fixed an issue in the receiver timestamping logic where the top 16-bits of the seconds field were held at zeros

 * Fixed XDC constraints around the handling of clock domain crossings in the receiver timestamping logic

AXI AHBLite Bridge (3.0)

 * Version 3.0

 * Removed output ports m_ahb_hclk and m_ahb_hresetn

 * Enhanced Support for IP Integrator

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI APB Bridge (3.0)

 * Version 3.0

 * Removed m_apb_pclk and m_apb_presetn ports.

 * Internal device family name change, no functional changes.

 * Error messaging related to memory addressing of apb_slave is improved in IP Integrator.

 * Virtex UltraScale Pre-Production Support.

AXI BFM Cores (5.0)

 * Version 5.0 (Rev. 2)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI BRAM Controller (4.0)

 * Version 4.0

 * The ID Ports s_axi_arid,s_axi_awid,s_axi_bid,s_axi_rid shall be generated only when the ID width is greater than or equal to '1'. when upgrading the previously released core, the ID ports mentioned above will not be generated unless the ID width is greater than or equal to '1'

 * Internal device family name change, no functional changes

AXI CAN (5.0)

 * Version 5.0 (Rev. 4)

 * Repackaged to improve internal automation, no functional changes

 * Internal device family name change, no functional changes

 * Updated example design to Synthesizable example design

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Virtex UltraScale Pre-Production support

AXI Central Direct Memory Access (4.1)

 * Version 4.1 (Rev. 2)

 * Example design updated to use blk_mem_gen_v8_2 and axi_traffic_gen_v2_0

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Chip2Chip Bridge (4.2)

 * Version 4.2

 * Added AURORA 64b66b 2-lane support

 * Included aurora do_cc and pma_init generation logic

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Clock Converter (2.1)

 * Version 2.1 (Rev. 2)

 * Internal device family name change, no functional changes

 * Updated IP-level XDC to reduce DRC warnings

 * Updated internal FIFO to fifo_generator_v12_0

 * Minor HDL cleanup on ACLK input to reduce warnings, no functional or QOR change.

AXI Crossbar (2.1)

 * Version 2.1 (Rev. 2)

 * Internal device family name change, no functional changes

 * FPGA primitive instantiations used only for 7 Series; changed to pure RTL for UltraScale and beyond.

 * Improved example design based on MI connectivity for more realistic waveforms.

AXI Data FIFO (2.1)

 * Version 2.1 (Rev. 2)

 * Internal device family name change, no functional changes

 * Updated internal FIFO to fifo_generator_v12_0

AXI Data Width Converter (2.1)

 * Version 2.1 (Rev. 2)

 * Internal device family name change, no functional changes

 * Updated IP-level XDC to reduce DRC warnings

 * Updated internal FIFOs to fifo_generator_v12_0 and blk_mem_gen_v8_2.

AXI DataMover (5.1)

 * Version 5.1 (Rev. 2)

 * ID Width related parameter have been made available in GUI

 * Minor RTL update to improve timing

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Direct Memory Access (7.1)

 * Version 7.1 (Rev. 2)

 * Example design updated to use blk_mem_gen_v8_2 and axi_traffic_gen_v2_0

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI EMC (3.0)

 * Version 3.0

 * Made the parity ports optional based on user selection.

 * Internal device family name change, no functional changes

 * Updated the example design to use Block Memory Generator version 8.2.

 * Virtex UltraScale Pre-Production support.

AXI EPC (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Ethernet (6.1)

 * Version 6.1

 * Support 1588 Correction Field format.

AXI Ethernet Buffer (2.0)

 * Version 2.0 (Rev. 2)

 * No changes

AXI Ethernet Clocking (2.0)

 * Version 2.0 (Rev. 1)

 * No changes

AXI EthernetLite (3.0)

 * Version 3.0

 * Improved GUI speed and responsiveness, no functional changes.

 * Added example design

 * Added demonstration testbench

 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI GPIO (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI HWICAP (3.0)

 * Version 3.0 (Rev. 4)

 * Updated example design to support Async mode

 * Internal device family name change, no functional changes

 * The Verilog file axi_hwicap_v3_0_icap_test.v is no longer delivered

 * Virtex UltraScale Pre-Production support.

AXI IIC (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI Interconnect (2.1)

 * Version 2.1 (Rev. 2)

 * Added support for automatic AXI MMU insertion to improve design correctness

AXI Interrupt Controller (4.1)

 * Version 4.1 (Rev. 1)

 * Allow changing C_IVAR_RESET_VALUE from the default value, to use C_BASE_VECTORS of the processor to initialize IVAR

 * Corrected OOC constraints

 * Modified block design propagation to support Concat v2.0

 * Internal device family name change, no functional changes

 * Removed unused WebTalk core generation information, no functional changes

AXI MMU (2.1)

 * Version 2.1

 * New IP Release (V2.1 designation indicates compatibility with existing AXI Interconnect V2.1 IP)

AXI Master Burst (2.0)

 * Version 2.0 (Rev. 4)

 * Repackaged to improve internal automation, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Master Lite (3.0)

 * Version 3.0 (Rev. 4)

 * Repackaged to improve internal automation, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Memory Mapped To PCI Express (2.3)

 * Version 2.3 (Rev. 1)

 * Removed dependency of AxRegion inputs

 * Added support for Zynq xc7z015 device

 * Added artix7l and aartix7 devices support for 35t, 75t, 50t

 * Added CPG236, CSG325 packages support

 * Base/High parameters of slave are set from IP bd.tcl instead of IP Integrator internal C++ function

 * AXI BRAM controller used in example design is changed from version 3.0 to 4.0

 * Fixed AXI upsizer module on read request to handle packet correctly.

 * Removed S6,V6 related files and instances.

 * Fixed FIFO full logic issue in cfg_event_handler

 * Fixed 62.5Mhz userclk1 for x1gen1 configuration when shared logic is selected in core

AXI Memory Mapped to Stream Mapper (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI Performance Monitor (5.0)

 * Version 5.0 (Rev. 2)

 * Repackaged to improve internal automation

 * AXI4LITE Monitoring support

 * Internal device family name change

 * Increased stream FIFO depth options.

 * Virtex UltraScale Pre-Production support

AXI Protocol Checker (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI Protocol Converter (2.1)

 * Version 2.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI Quad SPI (3.2)

 * Version 3.2

 * Repackaged to improve internal automation, no functional changes.

 * Some of the StartupE2/E3 signals are made available to user.

 * Constraints updated to take care of clock domain crossing.

 * Internal device family name change, no functional changes.

 * Spansion flash support added (beta).

 * Example design updated to use Block Memory Generator version 8.2.

 * Virtex UltraScale Pre-Production Support.

AXI Register Slice (2.1)

 * Version 2.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI TFT Controller (2.0)

 * Version 2.0 (Rev. 4)

 * Updated XDC constraints for asynchronous FIFO and out of context mode

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Timebase Watchdog Timer (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Timer (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

AXI Traffic Generator (2.0)

 * Version 2.0 (Rev. 2)

 * Repackaged to improve internal automation

 * Interface names are changed as below from 2013.2 to 2013.3 and beyond

 * axi_slave    -> S_AXI

 * axi_master   -> M_AXI

 * axis1_master -> M_AXIS_MASTER

 * axis2_master -> S_AXIS_MASTER

 * axis2_slave  -> S_AXIS_SLAVE

 * axi4_lite_m  -> M_AXI_LITE_CH1

 * New interfaces added as below from 2013.3 onwards

 * M_AXIS_SLAVE,M_AXI_LITE_CH2-5

 * Initialization file names are prepended with component name.

 * Fixed infinite transaction generation issue in streaming mode.

 * Internal device family name change

 * Redefined loop enable feature to loop read/write channels independently.

 * Additional TDATA widths supported for AXI4-Stream

 * Support for user specified TSTRB/TKEEP values for AXI4-Stream

 * Support added to stop traffic in HLTP->Data->Repetitive mode

 * Virtex UltraScale Pre-Production support

AXI UART16550 (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI USB2 Device (5.0)

 * Version 5.0 (Rev. 2)

 * Updated XDC constraints, no functional changes

 * Repackaged to improve internal automation, no functional changes

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Virtex UltraScale Pre-Production support

AXI Uartlite (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

AXI Video Direct Memory Access (6.2)

 * Version 6.2

 * Virtex UltraScale Pre-Production support

 * Enabled frame counter and delay counter function by default (by setting C_ENABLE_DEBUG_INFO_6, C_ENABLE_DEBUG_INFO_7, C_ENABLE_DEBUG_INFO_14 and C_ENABLE_DEBUG_INFO_15 to 1)

 * Helper core version update (fifo_generator_v12_0)

 * Repackaged to improve internal automation, no functional changes

 * Example design update to use blk_mem_gen_v8_2, axi_bram_ctrl_v4_0, axi_traffic_gen_v2_0

 * Internal device family name change, no functional changes

AXI Virtual FIFO Controller (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

AXI-Stream FIFO (4.0)

 * Version 4.0 (Rev. 4)

 * Internal device family name change, no functional changes

AXI4-Stream Accelerator Adapter (2.1)

 * Version 2.1

 * Added support for 8 inout scalar

 * Internal device family name change, no functional changes

AXI4-Stream Broadcaster (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Clock Converter (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

 * Fixed critical bug if using asynchronous mode when the number of synchronizer stages set to 2 (default.)  The value was being set to 1 in the core level wrapper, which will result in no synchronizer stages being used in the core.  This will increase MTBF failures.  The core has been fixed to the correct default value of 2.

AXI4-Stream Combiner (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Data FIFO (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Data Width Converter (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Interconnect (2.1)

 * Version 2.1 (Rev. 2)

 * Resolved internal bit-ordering with Snn_ARB_REQ_SUPPRESS signals.

AXI4-Stream Protocol Checker (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Register Slice (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Subset Converter (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream Switch (1.1)

 * Version 1.1 (Rev. 2)

 * Internal device family name change, no functional changes

AXI4-Stream to Video Out (3.0)

 * Version 3.0 (Rev. 4)

 * Added new parameter, Pixels Per Clock.

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Improved GUI speed and responsiveness, no functional changes

 * Internal device family name change, no functional changes

Accumulator (12.0)

 * Version 12.0 (Rev. 4)

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Fixed GUI bug which caused the GUI to hang when a parameter value outside the supported range was entered

 * Support for Virtex UltraScale devices at Pre-Production Status

Adder/Subtracter (12.0)

 * Version 12.0 (Rev. 4)

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * GUI bug fixed regarding the update of Latency when in Automatic latency configuration when widths changed.

 * display name changed from Adder Subtracter to Adder/Subtracter to match Product Guide.

 * Support for Virtex UltraScale devices at Pre-Production Status

Asynchronous Sample Rate Converter (2.0)

 * Version 2.0 (Rev. 3)

 * Repackaged to improve internal automation, no functional changes

Aurora 64B66B (9.2)

 * Version 9.2

 * Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup

 * Added support for UltraScale devices

 * Enhanced support for IP Integrator

 * Added Little endian support for data & flow control interfaces as non-default GUI selectable option

 * Interoperability guidance provided in Product Guide

 * Resolved functional issue seen with specific frame lengths in certain scenarios

 * Refer Product Guide for more information on critical warnings during IP upgrade

Aurora 8B10B (10.2)

 * Version 10.2

 * Added support for UltraScale devices

 * Added support for XC7Z015, XC7A50T, XC7A35T devices

 * Added support for automotive aArtix XA7A35, XA7A50T, XA7A75T & XA7A100T devices

 * Enhanced support for IP Integrator

 * Added Little endian support for data & flow control interfaces as non-default GUI selectable option

 * Fixed VHDL syntax issue on rxpmaresetdone_t signal for 7 Series based designs

 * Updated OOC XDC with all the available clocks for the selected IP configuration

 * Fixed TXCRC and RXCRC modules to operate upon valid data and report correct CRC status

 * Updated core reset logic with tx_lock synchronization

 * Updated the simplex timer values for 7 Series production silicon logic updates

 * Updated the hot-plug logic to handle clock domain crossing efficiently

 * Added recovery mechanism for channel bonding failure

Binary Counter (12.0)

 * Version 12.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

 * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral simulation and post- netlists. VCS version I-2014.03-Beta1 or later is recommended.

Block Memory Generator (8.2)

 * Version 8.2

 * Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices

 * Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices

 * Added support of the dynamic power saving for ultra-scale devices

 * Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7 Series devices

 * Internal device family name change, no functional changes

CIC Compiler (4.0)

 * Version 4.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

CORDIC (6.0)

 * Version 6.0 (Rev. 4)

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

CPRI (8.2)

 * Version 8.2

 * Updated to support version 6.0 of the CPRI specification.

 * Added 10.1376Gbps line rate support.

 * Added DRP access to the transceiver debug ports.

 * Added gt_reset_req_out port to cores with shared logic.

 * Added option to use QPLL1 in Ultrascale devices.

 * Transceiver output now inhibited when the core is disabled.

 * Core reset disabled when transceiver debug PRBS inputs are asserted.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

Chroma Resampler (4.0)

 * Version 4.0 (Rev. 4)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Bypass and test pattern modes are now working reliably

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Constraints syntax has been simplified, no functional changes

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Improved GUI speed and responsiveness, no functional changes

Clocking Wizard (5.1)

 * Version 5.1 (Rev. 2)

 * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock

 * Internal device family name change, no functional changes

Color Correction Matrix (6.0)

 * Version 6.0 (Rev. 4)

 * Bypass and test pattern modes are now working reliably

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

Color Filter Array Interpolation (7.0)

 * Version 7.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Bypass and test pattern modes are now working reliably

 * Constraints syntax has been simplified, no functional changes

Complex Multiplier (6.0)

 * Version 6.0 (Rev. 4)

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

Convolution Encoder (9.0)

 * Version 9.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

DDS Compiler (6.0)

 * Version 6.0 (Rev. 4)

 * sin_cos.vhd and sin_cos_quad_rast.vhd changed to work around simulation warnings. This change does not affect the behavior or performance of the core.

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

DSP48 Macro (3.0)

 * Version 3.0 (Rev. 5)

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

DUC/DDC Compiler (3.0)

 * Version 3.0 (Rev. 4)

 * Minor C model source code bug fix to support Visual Studio 2012 compiler, no functional changes

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Support for Virtex UltraScale devices at Pre-Production Status

Discrete Fourier Transform (4.0)

 * Version 4.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Support for obsolete Spartan devices removed from source code. Functionality of is unaffected.

 * Rephrasing of vhdl files. Functionality is unaffected.

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

DisplayPort (4.2)

 * Version 4.2 (Rev. 1)

 * Repackaged to improve internal automation, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Added support for XC7Z015 devices

 * XDC File updates for cross-clock paths

Distributed Memory Generator (8.0)

 * Version 8.0 (Rev. 4)

 * Internal device family name change, no functional changes

Divider Generator (5.1)

 * Version 5.1 (Rev. 2)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

 * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral sim and post- netlists. VCS version I-2014.03-Beta1 or later is recommended.

ECC (2.0)

 * Version 2.0 (Rev. 4)

 * Internal device family name change, no functional changes

Ethernet 1000BASE-X PCS/PMA or SGMII (14.2)

 * Version 14.2

 * Enabling SGMII over LVDS feature for UltraScale devices.

 * GT updates for Series-7 transceivers (Tx/Rx startup FSM updates).

 * Source of rxusrclk and rxusrclk2 for BASEX modes changed to rxoutclk instead of txoutclk.

 * Added missing XDC constraints  for rxoutclk in BASEX mode.

 * Change in definition of resetdone port.It now indicates the completion of rx and tx startup sequence.

 * Transceiver reset done indication gated with LINK_STATUS indication register.

 * Optional External MDIO interface added to control external phy,added optional parameter Ext_Management_Interface.

 * Changed EXAMPLE_SIMULATION Parameter from Boolean to Integer.

 * Freerunning clock of 50Mhz added for UltraScale devices for sgmii and basex modes .

 * Virtex UltraScale Pre-Production support added.

 * Internal device family name change, no functional changes.

 * Support for Zynq7015 device added.

Ethernet PHY MII to Reduced MII (2.0)

 * Version 2.0 (Rev. 4)

 * Added example design and demonstration testbench

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support.

FIFO Generator (12.0)

 * Version 12.0

 * Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.

 * Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.

 * Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices

 * Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices

 * Internal device family name change, no functional changes

FIR Compiler (7.1)

 * Version 7.1 (Rev. 3)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Fixed AR58946, COE file coefficient specification now working correctly in IP Integrator.

 * Support for Virtex UltraScale devices at Pre-Production Status

Fast Fourier Transform (9.0)

 * Version 9.0 (Rev. 4)

 * Removed duplicate VHDL process from Radix-2 architecture which caused multiple driver synthesis errors with Vivado 2014.1

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Rephrasing code in file r22_twos_comp_mux.vhd. Functionality is unchanged.

 * Rephrasing code in file xfft_v9_0_viv.vhd. Functionality is unchanged.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

Fixed Interval Timer (2.0)

 * Version 2.0 (Rev. 3)

 * Internal device family name change, no functional changes

Floating-point (7.0)

 * Version 7.0 (Rev. 4)

 * GUI fix to disable internal debug messages from Accumulator

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Rephased RTL in file flt_round_dsp_opt_full.vhd. Functionality is unaffected.

 * Internal device family name change, no functional changes

 * Corrected parameter order and comments for Accumulator operator in allfns.c

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

 * Added attribute in flt_log_addsub_taylor_fabric.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged.

G.709 FEC Encoder/Decoder (2.1)

 * Version 2.1 (Rev. 1)

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * demonstration testbench changed to prevent integer overflow in XSIM for random seeds.

 * Support for Virtex UltraScale devices at Pre-Production Status

 * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral sim and post- netlists. VCS version I-2014.03-Beta1 or later is recommended.

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

 * Version 1.0 (Rev. 4)

 * Standardized instance name in demonstration testbench, no functional changes

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

 * Version 2.0 (Rev. 4)

 * Minor C model source code bug fix to support Visual Studio 2012 compiler, no functional changes

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

Gamma Correction (7.0)

 * Version 7.0 (Rev. 4)

 * Bypass and test pattern modes are now working reliably

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

Gmii to Rgmii (3.0)

 * Version 3.0 (Rev. 1)

 * Added library path for vhdl for VCS support.

High Speed SelectIO Wizard (1.0)

 * Version 1.0

 * Initial release

 * Internal device family name change, no functional changes

IBERT 7 Series GTH (3.0)

 * Version 3.0 (Rev. 4)

 * Repackaged to improve internal automation, no functional changes

IBERT 7 Series GTP (3.0)

 * Version 3.0 (Rev. 4)

 * Added new device support for AArtix7, Artix7L, QArtix7 families

 * Added the package 'csg325 fgg484 fgg676 fbg676 fbg484 clg484 sbg484 rb484 rb676 rs484

 * Repackaged to improve internal automation, no functional changes

IBERT 7 Series GTX (3.0)

 * Version 3.0 (Rev. 4)

 * Repackaged to improve internal automation, no functional changes

IBERT 7 Series GTZ (3.1)

 * Version 3.1 (Rev. 2)

 * Added New FLG package support. Removed support for unsupported packages xc7vh580t-hcg1932, xc7vh870t-hcg1931

IBERT UltraScale GTH (1.0)

 * Version 1.0

 * Native Vivado Release

ILA (Integrated Logic Analyzer) (4.0)

 * Version 4.0

 * Updated the IP to support new DBG_HUB stitcher algorithm

 * Updated ILA AXI monitor feature to the IP

 * Internal device family name change, no functional changes

IOModule (2.2)

 * Version 2.2 (Rev. 1)

 * Modified block design propagation to support Concat v2.0

 * Added warning for invalid C_MASK and C_IO_MASK parameter user override

 * Changed internal address automation, no functional changes

 * Internal device family name change, no functional changes

 * Removed unused WebTalk core generation information, no functional changes

Image Enhancement (8.0)

 * Version 8.0 (Rev. 3)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Bypass and test pattern modes are now working reliably

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Constraints syntax has been simplified, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Improved GUI speed and responsiveness, no functional changes

Interlaken (1.1)

 * Version 1.1

 * GTH Implementation on XCVU095-FFVD1924 device without bitstream support. This is due to the timing information not being accurate; designs may fail timing

 * GTY simulation only

 * Lane rates supported 12x12.5G, 6x25G

 * Synchronous / Asynchronous Clocking mode

 * MetaFrame 256 upto 8192

 * OOBFC for different calendar lengths

 * IBFC for different calendar lengths

 * Shared Logic in core / example design

 * XSIM / Questa (10.2a) / VCS (H-2013.06-sp1) / IES (12-20.016)

Interleaver/De-interleaver (8.0)

 * Version 8.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex Ultrascale devices at Pre-Production Status

 * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral simulation and post- netlists. VCS version I-2014.03-Beta1 or later is recommended.

JESD204 (5.2)

 * Version 5.2

 * Added GUI option to select on which clock edge SYSREF is sampled

 * Added GUI option for UltraScale devices to select between CPLL and QPLL0

 * Added AXI register to enable skewing of SYSREF

 * Added AXI register to read back value of SYNC

 * Added AXI register to read back if a valid SYSREF had been captured

 * Added AXI register to determine behavior of SYNC after core has dropped out of sync

 * 9, 10, 11 and 12 Lane support added (excluding Artix). Additional pins required for the third QUAD (PLL2) have been added to GTX and GTH to support up to 12 lanes.

 * Artix XC7A35T, XC7A50T and XC7A75T support added (check DS180 for the maximum number of GTPs available in each part/package)

 * The AXI IPIF interface no longer uses the proc_common library which reduced the number of unused RTL filed delivered with the core

 * Fixed behavior of tx_tvalid not being correctly asserted under certain conditions. (AR 58747)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Removed optional port gt*_txphaligndone_out. Affects 7 series configurations with transceiver debug ports enabled

 * Removed optional port gt*_rxcdrlock_out. Affects 7 series configurations with transceiver debug ports enabled

JTAG to AXI Master (1.0)

 * Version 1.0 (Rev. 2)

 * Local ARESETN generation for example design in top HDL

 * Internal device family name change, no functional changes

 * Updated xsdb slave to 3.0, FIFO generator to 12.v

 * Support for full bandwidth for JTAG_AXI AXI4 burst write/read transaction.

LMB BRAM Controller (4.0)

 * Version 4.0 (Rev. 3)

 * Changed internal address automation, no functional changes

 * Internal device family name change, no functional changes

 * Added warning for invalid C_MASK parameter user override

LTE DL Channel Encoder (3.0)

 * Version 3.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

LTE Fast Fourier Transform (2.0)

 * Version 2.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Rephrasing code in file r22_twos_comp_mux.vhd. Functionality is unchanged.

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

 * Added attribute in dit_burst_datapath.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged.

LTE PUCCH Receiver (2.0)

 * Version 2.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

LTE RACH Detector (2.0)

 * Version 2.0 (Rev. 4)

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Clarified derivation of "Fc" register setting in run_bitacc_cmodel.c - no change to functionality.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

 * The C model is not bit accurate to the behavior of the RTL, netlist models or hardware. AR56292

LTE UL Channel Decoder (4.0)

 * Version 4.0 (Rev. 4)

 * Minor C model source code bug fix to support Visual Studio 2012 compiler, no functional changes

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

Local Memory Bus (LMB) 1.0 (3.0)

 * Version 3.0 (Rev. 3)

 * Updated constraints to support UltraScale

 * Internal device family name change, no functional changes

Mailbox (2.1)

 * Version 2.1

 * Changed internal address automation, no functional changes

 * Added parameter for number of synchronization flip-flops in asynchronous configuration

 * Internal device family name change, no functional changes

Memory Interface Generator (MIG 7 Series) (2.0)

 * Version 2.0 (Rev. 3)

 * Extended IES and VCS support to Multi-Controller and Multi-Interface designs

 * Added Support for Artix XC7A35T and XC7A50T devices (Xilinx Answer 59632)

 * Resolved recustomization and file generation issue (Xilinx Answer 59714)

 * Resolved Vivado not generating correct VHDL template issue (Xilinx Answer 59515)

 * Resolved inability to derive 150MHz input clock frequency issue (Xilinx Answer 58647)

 * Resolved IP generation error message for 8Gb part (Xilinx Answer 58894)

 * Resolved non-ideal RC settings for DIMMs (Xilinx Answer 57221)

 * Resolved timing failures with the VIO/ILA 2.0 cores when using multiple clock domains (Xilinx Answer 56387)

 * Added stand-alone support for XSIM through Vivado (Xilinx Answer 58668)

 * Resolved VCS and IES simulation failures (Xilinx Answer 58636)

 * Resolved RLDRAM3 simulation failures (Xilinx Answer 58635)

 * Resolved RLDRAM3 memory model out of date (Xilinx Answer 58620)

Memory Interface Generator (MIG) (5.0)

 * Version 5.0

 * Support of AXI for DDR3 and DDR4 interfaces

 * Support of QDRII+ Interface

 * IP Integrator Support

 * Removal of parity port for DDR4 interface

MicroBlaze (9.3)

 * Version 9.3

 * Added debug enhancements: Program Trace, Performance Monitoring, Non-intrusive Profiling and Cross Trigger support

 * Updated OOC constraints to include debug clocks

 * Removed unused code and signals to improve coverage metrics

 * Fixed issue causing an incorrect vector for External Non-maskable Break. Versions that have this issue: 9.2, 9.1, 9.0, 8.50.c, 8.50.b, 8.50.a, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a, 8.00.b, 8.00.a, 7.30.b, 7.30.a, 7.20.d, 7.20.c, 7.20.b, 7.20.a, 7.10.d, 7.10.c, 7.10.b, 7.10.a, 7.00.b, 7.00.a. Can only occur when area optimization is enabled.

 * Ensure that AXI4-Stream get instructions with exceptions never write to the destination register. Versions that have this issue: 9.2, 9.1, 9.0, 8.50.c, 8.50.b, 8.50.a, 8.40.b, 8.40.a, 8.30.a. Can only occur when area optimization is enabled.

 * Internal device family name change, no functional changes

 * Removed unused WebTalk core generation information, no functional changes

MicroBlaze Debug Module (MDM) (3.1)

 * Version 3.1

 * Added support for debug register access from AXI

 * Added support for AXI memory access from debug

 * Added cross trigger support

 * Internal device family name change, no functional changes

MicroBlaze MCS (2.2)

 * Version 2.2

 * Increased available memory sizes

 * Added option to use MicroBlaze Debug Module (MDM) UART for serial I/O via JTAG

 * Updated with latest subcore versions

 * Added XDC constraints for internal debug clocks

 * Internal device family name change, no functional changes

Multiplier (12.0)

 * Version 12.0 (Rev. 4)

 * Core will always deliver an ooc_xdc file, even when PipeStages (latency) = 0.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

Multiply Adder (3.0)

 * Version 3.0 (Rev. 4)

 * Core will now deliver an ooc_xdc file, without constraints, when latency is zero.

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

Mutex (2.1)

 * Version 2.1

 * Changed internal address automation, no functional changes

 * Added parameter for number of synchronization flip-flops in asynchronous configuration

 * Internal device family name change, no functional changes

Peak Cancellation Crest Factor Reduction (5.0)

 * Version 5.0 (Rev. 1)

 * Standardized instance name in demonstration testbench, no functional changes

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Fixes for Warning Reduction, speed optimization

 * Support for Virtex UltraScale devices at Pre-Production Status

Processor System Reset (5.0)

 * Version 5.0 (Rev. 4)

 * Internal device family name change, no functional changes

QSGMII (3.2)

 * Version 3.2

 * GT updates for Series-7 transceivers (Tx/Rx startup FSM updates).

 * Change in definition of resetdone port.It now indicates the completion of rx and tx startup sequence.

 * Internal device family name change, no functional changes

RAM-based Shift Register (12.0)

 * Version 12.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Support for Virtex UltraScale devices at Pre-Production Status

RGB to YCrCb Color-Space Converter (7.1)

 * Version 7.1 (Rev. 2)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Removed PDF document that provide the product guide redirect link

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

RXAUI (4.2)

 * Version 4.2

 * Virtex UltraScale Pre-Production support

 * Added support for extra Artix-7 devices (by enabling support for low-cost wire-bonded packages)

 * Fixed the operation of the mgt_rx_reset_inprocess signal (part of the GTPE2/GTHE2 reset logic)(Xilinx Answer 59860)

 * Fixed GTPE2 reliability issues by ensuring that the GTPE2 cannot get permanently stuck in the wrong internal datawidth setting during reset cycles. (Xilinx Answer 59861)

 * Fixed powerdown reliability issues by ensuring that the transceiver phase alignment state machine is reset when the powerdown state is removed. (Xilinx Answer 59292)

 * Fixed the SIM_RESET_SPEEDUP attribute setting (now set to FALSE) for GTPE2 and GTHE2 transceivers, as per the 7 Series FPGAs Transceivers User Guides.  This is required in order to simulate correctly the transceiver reset/initialization sequence; this leads to longer reset/initialization simulation times.

 * Added missing pll0outrefclk_out port to the IP GUI customization symbol and IP integrator symbol diagrams.  This port is now present for Artix-7 designs when the shared logic is included in the core

 * Corrected the UltraScale transceiver debug port widths in the IP GUI customization symbol and IP integrator symbol diagrams

 * Added clock frequency metadata to the Quad PLL and GT reference clocks for use in IP Integrator only

 * Added missing XDC constraints on the MDIO signal inputs to ease timing closure (Xilinx Answer 59914)

 * Added missing powerdown signals from the core to the UltraScale transceiver

 * Corrected the mgt_txcharisk signal assignment in Verilog projects for UltraScale devices

 * Corrected the 7 Series transceiver debug port rxcdrhold to route to the transceiver

 * Added commented example of GT placement in example design XDC

 * Internal device family name change, no functional changes

Reed-Solomon Decoder (9.0)

 * Version 9.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

Reed-Solomon Encoder (9.0)

 * Version 9.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

S/PDIF (2.0)

 * Version 2.0 (Rev. 4)

 * Added core xdc constraints including helper core (fifo_generator) constraints

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Example design update to make it synthesizable

 * Virtex UltraScale Pre-Production support

SDI RX to Video Bridge (1.0)

 * Version 1.0 (Rev. 2)

 * GUI format upgrade

SMPTE 2022-1/2 Video over IP Receiver (1.0)

 * Version 1.0 (Rev. 2)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

SMPTE 2022-1/2 Video over IP Transmitter (1.0)

 * Version 1.0 (Rev. 2)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

SMPTE SD/HD/3G-SDI (3.0)

 * Version 3.0 (Rev. 1)

 * Repackaged to improve internal automation, no functional changes

SMPTE2022-5/6 Video over IP Receiver (3.0)

 * Version 3.0 (Rev. 4)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

SMPTE2022-5/6 Video over IP Transmitter (3.0)

 * Version 3.0 (Rev. 4)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * VID_LOCK_PARAM register move from 0x0148 to 0x0160

SPI-4.2 (13.0)

 * Version 13.0 (Rev. 4)

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

SelectIO Interface Wizard (5.1)

 * Version 5.1 (Rev. 1)

 * Repackaged to improve internal automation, no functional changes

 * Updated Clock Signaling enablement in GUI for non Custom Interface Templates

Serial RapidIO Gen2 (3.1)

 * Version 3.1 (Rev. 1)

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Repackaged to improve internal automation, no functional changes

Soft Error Mitigation (4.1)

 * Version 4.1

 * Added support for xc7a35t, xc7a50t, xa7a35t, xa7a50t, and xa7a75t devices at Pre-Production status.

 * Replaced injection shim option "ChipScope" with "Vivado Lab Tools".

 * Improved efficiency of behavioral simulation.

 * Added simulation test harness to demonstrate inclusion of the IP in a project using Vivado simulation flows. IP behaviors are not observable in simulation. Hardware-based evaluation is required.

System Cache (3.0)

 * Version 3.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Removed unused WebTalk core generation information, no functional changes

 * Adjusted RTL attributes to enable better quality of result, no functional changes

System Management Wizard (1.0)

 * Version 1.0 (Rev. 1)

 * Internal device family name change, no functional changes

Ten Gigabit Ethernet MAC (13.1)

 * Version 13.1

 * Virtex UltraScale Pre-Production support.

 * Added an option for support of Priority Based Flow Control.

 * Reduced the transmitter data path latency by 57.6 ns.  This is achieved via a new CRC engine architecture.

 * Updated Statistics to correctly differentiate between small and fragment frames (AR 59308).

 * Updated TX Statistics vector to correctly indicate frame size for oversize frames.

 * Fix for corner case incorrect RX statistics vector bit 27 when runt frame received.

 * Fix for corner case illegal Control characters before the Start code of a transmitted frame

 * Fix for corner case illegal IFG before the Start code of a transmitted frame.

 * Fix for corner case TX frame error due to previous frame being close to the maximum frame size.

 * Ensured Custom Preamble enable is correctly reset.

 * Added missing XDC constraints on the MDIO signal inputs to ease timing closure (AR 59891).

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Enhanced the example design demonstration testbench with a CRC engine. Frames of any size or content can now be generated to stimulate the core.

 * Removed an unused HDL source file from the core (synchronizer_e.vhd).

 * Added serialization logic on the tx_statistics_vector and rx_statistics_vector outputs in the example design to reduce the pinout.

 * Internal device family name change, no functional changes

Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (4.1)

 * Version 4.1 (Rev. 1)

 * Virtex UltraScale Pre-Production support

 * Fixed an issue in Verilog Vivado projects for BASE-KR with Auto-negotiation enabled and no MDIO Management, where Link Training would not start automatically (AR 59904)

 * Fixed an issue where a 'soft' PMA or PCS reset would cause the MDIO interface logic to be reset, possibly during an MDIO access, and so possibly missing the MDIO operation (AR 59910)

 * Added a 750ms watchdog timer to the Block level which will reset the RX side of the transceiver if PCS Block Lock is not attained within 750ms (AR 59911)

 * Added ASYNC_REG attributes to additional registers to enable better packing of synchronizer register stages

 * UltraScale only - Added progdivreset control for BASE-R cores and added BUF_GT reset to the RXUSRCLK path BUFG_GT

 * UltraScale only - Changed Core PCS Reset to toggle the transceiver PCS Resets instead of the progdivresets

 * UltraScale only - Edited XDC create_clock constraints to work with the latest Vivado tools which now trace clock generation through the GTHE3_CHANNEL block

 * Changed some internal register names to allow MultiCyclePath constraints from the RX Decoder to RX Elastic Buffer to take effect and to ease timing closure

 * Added additional MultiCyclePath constraints to catch a few paths which were being timed at full rate to ease timing closure

 * Removed an unnecessary constraint on refclk_n clock pin, in the ooc.xdc file.

 * Moved transceiver refclk definition to the core XDC file when Shared Logic is selected

 * Fixed typo in the core_to_gt_drp interface for the core_to_gt_drpaddr port to fix the cores GUI symbol and connectivity in IP Integrator designs

 * Added dependency code to all interfaces to fix the cores GUI symbol in IP Integrator designs

 * Added tie-off defaults for DRP input ports, for IP Integrator designs only

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Reduced the number of Warnings from Vivado when using this core

 * Added synchronizers to the (constant) timer_125us_cycles value to stop DRC violations

 * Core GUI updated to include a message about BASE-R being a free unlicensed core

 * Internal device family name change, no functional changes

Test Pattern Generator (6.0)

 * Version 6.0

 * Internal device family name change, no functional changes

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Constraints syntax has been simplified, no functional changes

 * A Video Timing Controller interface added

 * Noise generation changed to give a more Gaussian distribution

Timer Sync 1588 (1.2)

 * Version 1.2

 * Added support for an alternative 64-bit fractional nanoseconds timer format.

 * Internal device family name change, no functional changes

Tri Mode Ethernet MAC (8.2)

 * Version 8.2

 * Added Priority Flow Control (PFC) support

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Virtex UltraScale Pre-Production support

 * Increased the number of configurable filters to 16

 * Fixed bug in the UltraScale RGMII Transmitter logic which prevented the TX error signal from MAC from being propagated to RGMII TX_CTL output

 * Enabled cascading of ODELAYE3 for RGMII TXC output for UltraScale devices

 * Added set_false_path constraint to input of recently added reset synchronizer

 * For Zynq device 7z010, the IO-Standard and Pin-Location constraints are not generated in the example design XDC

 * Modified Block XDC constraints to use get_pins instead of get_nets for multicycle paths through MDIO, MDC

 * In example design, added the missing after clause for signal assignment

 * In example design, corrected vector widths in conditional expression

UltraScale FPGAs Transceivers Wizard (1.2)

 * Version 1.2

 * Added several new transceiver configuration preset options

 * Added support for behavioral HDL simulation of configurations utilizing GTY transceivers

 * Added support for Cadence IES and Synopsys VCS simulators to existing support for Mentor Graphics Questa and Xilinx Vivado Simulator

 * Added support for SATA configurations

 * Enabled the ability to configure the secondary QPLL when one QPLL type is used

 * Enabled the ability to select the frequency of TXOUTCLK when the TX programmable divider is used

 * Enabled the ability to locate the reset controller helper block inside the core irrespective of transceiver common location

 * Improved performance and reliability of GTH transceivers in Kintex UltraScale ES1 devices via parameter updates and CPLL calibration

 * Improved resource utilization in raw mode and 8B/10B example design configurations

 * Fixed an issue where certain complex reference clock routing configurations could lead to routing congestion

 * Internal device family name change, no functional changes

UltraScale FPGA Gen3 Integrated Block for PCI Express (3.0)

 * Version 3.0

 * Changed Internal device family name, no functional changes

 * Added Root port configuration support

 * Added IP I ntegratorsupport

 * Integrated GT Wizard

 * Added external PIPE Interface support

 * Added shared logic support

 * Added optional transceiver control and status ports

 * Added dynamic module naming to avoid name conflict when multiple cores are generated

 * Enabled multiple PCIe blocks for Kintex UltraScale and Virtex UltraScale devices

 * Added support for industrial speed grade parts

 * Added support to use dedicated system reset routing for the PCIe_X0Y0 hardblock (enabled by default) except for xcvu065 and xcvu095 devices

 * Added a dedicated routing input port and renamed passthrough routing output ports (pcie_perstn* ports)

 * Added support to specify the reset polarity for the sys_reset port (Active Low by default)

 * The default reset polarity has been changed from Active High to Active Low

VIO (Virtual Input/Output) (3.0)

 * Version 3.0 (Rev. 2)

 * Kintex UltraScale support

 * xsdb stitching enhancements

 * Internal device family name change, no functional changes

Video Deinterlacer (4.0)

 * Version 4.0 (Rev. 4)

 * Fixed demo testbench with correct register setting that allow bypass mode work properly

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

Video In to AXI4-Stream (3.0)

 * Version 3.0 (Rev. 4)

 * Added new parameter, Pixels Per Clock.

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Improved GUI speed and responsiveness, no functional changes

 * Internal device family name change, no functional changes

Video On Screen Display (6.0)

 * Version 6.0 (Rev. 4)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

Video Scaler (8.1)

 * Version 8.1 (Rev. 3)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Constraints syntax has been simplified, no functional changes

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * Added Automatic Lanzcos coefficient generation to the GUI

 * Simulation warnings reduced for data width of 10 used in the GUI

 * Fixed coe to mif file conversion in the GUI for negative coefficient values

Video Timing Controller (6.1)

 * Version 6.1 (Rev. 1)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * Internal device family name change, no functional changes

 * Bypass and test patterns modes for the video cores that use the v_tc_v6_1 core now work reliably

Video to SDI TX Bridge (1.0)

 * Version 1.0 (Rev. 2)

 * Improved GUI speed and responsiveness, no functional changes

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (3.0)

 * Version 3.0 (Rev. 1)

 * Enabled Tandem configuration support for 330T and 980T devices

 * Fixed HDL uniquification issue

 * Changed the directory structure of the core without affecting the design hierarchy

Viterbi Decoder (9.0)

 * Version 9.0 (Rev. 4)

 * Internal device family name change, no functional changes

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

 * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected.

 * Support for Virtex UltraScale devices at Pre-Production Status

XADC Wizard (3.0)

 * Version 3.0 (Rev. 3)

 * Internal device family name change, no functional changes

 * Corrected GUI enablement option in Default sequencer mode

XAUI (12.1)

 * Version 12.1 (Rev. 1)

 * Virtex UltraScale Pre-Production support

 * Fixed the operation of the mgt_rx_reset_inprocess signal (part of the GTPE2/GTHE2 reset logic)(Xilinx Answer 59860)

 * Fixed GTPE2/GTHE2 reliability issues by ensuring that the GTPE2/GTHE2 cannot get permanently stuck in the wrong internal datawidth setting during reset cycles. (Xilinx Answer 59861)

 * Fixed powerdown reliability issues by ensuring that the transceiver phase alignment state machine is reset when the powerdown state is removed. (Xilinx Answer 59292)

 * Fixed the SIM_RESET_SPEEDUP attribute setting (now set to FALSE) for GTPE2 and GTHE2 transceivers, as per the 7 Series FPGAs Transceivers User Guides.  This is required in order to simulate correctly the transceiver reset/initialization sequence; this leads to longer reset/initialization simulation times.

 * Increased the clock domain crossing synchronizer flip-flop stages for 20 Gigabits per second operation.

 * Added missing XDC constraints on the MDIO signal inputs to ease timing closure (Xilinx Answer 59912)

 * Added clock frequency metadata to the GT reference clocks for use in IP Integrator only.

 * Updated the description in the Vivado IP catalogue to state that the core can support 20 Gigabits per second operation.

 * Internal device family name change, no functional changes

YCrCb to RGB Color-Space Converter (7.1)

 * Version 7.1 (Rev. 2)

 * Virtex UltraScale Pre-Production support

 * Defense-grade Artix-7Q, Kintex-7Q, Virtex-7Q and Zynq-7000Q Production support

 * C models for Windows are compiled using Microsoft Visual Studio 2012

 * Internal device family name change, no functional changes

 * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done

 * Enable third party synthesis tools to read encrypted netlists (but not source HDL)

ZYNQ7 Processing System (5.4)

 * Version 5.4

 * IRQ_F2P connections to be made directly in the silicon

ZYNQ7 Processing System BFM (2.0)

 * Version 2.0 (Rev. 2)

 * Changed the input port width in fixed value 3

interrupt_controller (3.0)

 * Version 3.0 (Rev. 1)

 * Virtex UltraScale Pre-Production support

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54480 LogiCORE IP JESD204B - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 59986
Date 05/12/2017
Status Active
Type Release Notes
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite
IP
  • Audio, Video, and Image Processing
  • Automotive
  • Basic Logic
  • More
  • Bus Interface and IO
  • Communication and Networking
  • Digital Signal Processing
  • FPGA Features and Debug
  • Interconnect Infrastructure
  • Math
  • Memory Interface and Storage Element
  • Less
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