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AR# 59988

Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Out of the box example design simulation fails with 'Address Aligned' mode for 256-bit AXI Interface and 64-bit BAR configuration

Description

Version Found: v3.0
Version Resolved and other Known Issues: See (Xilinx Answer 54645)

When simulating the Virtex-7 FPGA Gen3 Integrated Block for PCI Express example design with the core generated with 'Address Aligned' mode, 256-bit AXI Interface and 64-bit BAR configuration, the simulation ends with the following error message:

"TIMEOUT ERROR in usrapp_tx:TSK_WAIT_FOR_READ_DATA.  Completion data never received."

Solution

This is a known issue and is scheduled to be fixed in the next release of the core. 

To work around the issue, please copy the attached files pci_exp_ursapp_tx.v and sample_tests.vh into 'dsport' and 'tests' directories respectively in the generated project directory.

Note: "Version Found" refers to the version where the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
04/16/2014 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
sample_tests.vh 17 KB VH
pci_exp_usrapp_tx.v 186 KB V
AR# 59988
Date Created 03/28/2014
Last Updated 04/17/2014
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)