UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59989

MIG Ultrascale - Critical warnings are generated when multiple MIG instances are included in a design

Description

Version Found: v5.0
Version Resolved: See (Xilinx Answer 58435)

When a design has multiple MIG instances included in the same design AND they have Out-of-Context (OOC) disabled for each instance the below critical warnings are seen due to same file name being used in both of the MIG cores:

CRITICAL WARNING: [filemgmt 20-1741] File "riuMap.vh" is used by both "mig_0" and "mig_1", but with different contents. This may lead to unpredictable results.
Please use the report_ip_status command to resolve the differences or synthesize the modules independently. (Files are: "/proj/dsv_xhd/pparata/work/temp/run/multi_mig/example_top/mig_0_example/mig_0_example.srcs/sources_1/ip/mig_0/rtl/map/riuMap.vh" and "/proj/dsv_xhd/pparata/work/temp/run/multi_mig/example_top/mig_0_example/mig_0_example.srcs/sources_1/ip/mig_1/rtl/map/riuMap.vh")


CRITICAL WARNING: [filemgmt 20-1741] File "ddrMapDDR4.vh" is used by both "mig_0" and "mig_1", but with different contents. This may lead to unpredictable results.
Please use the report_ip_status command to resolve the differences or synthesize the modules independently. (Files are: "/proj/dsv_xhd/pparata/work/temp/run/multi_mig/example_top/mig_0_example/mig_0_example.srcs/sources_1/ip/mig_0/rtl/map/ddrMapDDR4.vh" and "/proj/dsv_xhd/pparata/work/temp/run/multi_mig/example_top/mig_0_example/mig_0_example.srcs/sources_1/ip/mig_1/rtl/map/ddrMapDDR4.vh")


CRITICAL WARNING: [filemgmt 20-1741] File "iobMapDDR4.vh" is used by both "mig_0" and "mig_1", but with different contents. This may lead to unpredictable results.
Please use the report_ip_status command to resolve the differences or synthesize the modules independently. (Files are: "/proj/dsv_xhd/pparata/work/temp/run/multi_mig/example_top/mig_0_example/mig_0_example.srcs/sources_1/ip/mig_0/rtl/map/iobMapDDR4.vh" and "/proj/dsv_xhd/pparata/work/temp/run/multi_mig/example_top/mig_0_example/mig_0_example.srcs/sources_1/ip/mig_1/rtl/map/iobMapDDR4.vh")


Solution

This issue only occurs when OOC is disabled. 

To work around the issue enable OOC for each MIG instance or use the following manual work-around:

  1. Manually change all MIG RTL files except <core_name>.sv, and <core_name>_mig.sv for each instance of the controllers to make the name unique.
    Then modify the instantiation name inside each module where these files are instantiated.

  2. Update the <core_name>.xml file with each of the new unique names.

  3. Manually modify the location of the BUFG for one of the controllers. 
    The BUFG allocations of multiple controllers cannot be within the same vertical line. 
    One of the controller's BUFGs must be moved to a different vertical line. 
    If assistance is needed, please open a webcase.

Revision History:
07.08/2014 - Updated manual work around steps

04/16/2014 - Initial Release

Linked Answer Records

Master Answer Records

AR# 59989
Date Created 03/28/2014
Last Updated 07/08/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale