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AR# 60015

2014.1 Vivado Synthesis - ERROR: [Synth 8-550] port width mismatch in instance array for port 'din[a]'

Description

The following usage of instance array in SystemVerilog causes an error in Vivado Synthesis.

Example code:

typedef enum logic [1:0] {s0, s1, s2, s3} enum_t;
typedef struct packed {
  logic [7:0] a;
  enum_t x;
  logic b;
} struct_t;
module top (
            input struct_t din [1:0],
            input struct_t dout [1:0]
           );
struct_t din_0,din_1;
struct_t dout_0,dout_1;
sub u[1:0] (
            .din({din_0,din_1}),
            .dout({dout_0,dout_1})
           );
assign din_0 = din[0];
assign din_1 = din[1];
assign dout[0] = dout_0;
assign dout[1] = dout_1;
endmodule
module sub (
            input struct_t din,
            output struct_t dout
           );
assign dout = din;
endmodule

Vivado Synthesis is not able to resolve the port width mapping in the instance array when accessing the structure.

ERROR: [Synth 8-550] port width mismatch in instance array for port 'din[a]': actual width = 22, formal width = 8, instance count = 2  [XX/top.sv:36]

Solution

Currently the structure type of port map in instance array is not supported in Vivado Synthesis. 

This will be supported in a future release.

AR# 60015
Date Created 03/30/2014
Last Updated 04/16/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1