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AR# 60030

2014.1 - IBERT - DRC violation Error: [Drc 23-20] during bitstream generation


Bitstream generation for the GTP example design fails with following DRC Error message:

ERROR: [Drc 23-20] Rule violation (REQP-1584) GT PLLLOCKDETCLK can not be REFCLK - GTPE2_COMMON pin u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtpe2_common/PLL0LOCKDETCLK cannot be driven by a clock derived from the same clock used as the reference clock for the PLL, including TXOUTCLK*, RXOUTCLK*, the output from the IBUFDS_GTE2 providing the reference clock, and any buffered or multiplied/divided versions of these clock outputs. Please see UG482 for more information. Source, through a clock buffer, is the same as the GT cell reference clock.


To work around this issue, set the Vivado Synthesis option -flattern_hierarchy to 'none' before running synthesis. 

This is a known issue which will be addressed in a future release.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
52257 What is the function of the Vivado Synthesis -flatten_hierarchy switch, and what are its various options? N/A N/A
AR# 60030
Date Created 03/31/2014
Last Updated 05/21/2014
Status Active
Type General Article
  • Kintex-7
  • Artix-7
  • Virtex-7