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AR# 60050

MIG 7 Series DDR3/DDR2 - cmp_data_r and dbg_rddata_r are not aligned

Description

Version Found: MIG 7 Series v2.0
Version Resolved: See (Xilinx Answer 54025)

The MIG 7 Series generated example design contains a traffic generator which can detect data errors.

When looking at the compared data "cmp_data_r" vs. the actual read data "dbg_rddata_r" they appear misaligned but no compare errors are detected.

Solution

This is safe to ignore as the internal compare logic is correctly aligned and comparing the correct data.

This can be difficult to characterize if actual data errors occur.

The misalignment between cmp_data_r and dbg_rddata_r should not be more than 5 cycles off so careful attention is required to determine which cycle cmp_data_r should actually be used to compare against dbg_rddata_r.

Revision History
04/16/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 60050
Date Created 04/01/2014
Last Updated 04/16/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series