UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60061

Vivado Synthesis - INIT value of Inferred dynamic SRL is not correct

Description

Vivado Synthesis infers dynamic SRL from the below HDL code but the INIT value of the SRL is incorrect in the netlist.

The INIT value is expected to be 16'hFFFF, but is instead 16'h0000.

////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module test (input A0, A1, A2, A3, 
                    input CE, 
                    input CLK, 
                    input D, 
                    output Q);

reg [15:0] shift_reg;
initial
shift_reg [15:0] = 16'hFFFF;
  
wire [3:0] addr = {A3, A2, A1, A0};
always @ (posedge CLK) begin
  if (CE)
    shift_reg <= ({(shift_reg[14:0]), D});
end
assign Q = shift_reg[addr];
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////

Solution

The register initialization method in this code is not supported.

To get around the issue, specify the initial value of the register with the register declaration as below:

reg [15:0] shift_reg = 16'hFFFF;

AR# 60061
Date Created 04/01/2014
Last Updated 10/08/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2014.1