UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60072

Ultrascale FPGA Gen3 Integrated Block for PCI Express v3.0 - Timing Violations with non X0Y0 PCIe locations

Description

Version Found: 3.0
Version Resolved and other known issues: (Xilinx Answer 57945)

When implementing a design with the Ultrascale FPGA Gen3 Integrated Block for PCI Express v3.0 core, some timing violations have been observed if non X0Y0 PCIe locations are selected.

Solution


This is a known issue in Vivado 2014.1 to be fixed in a future release of the core. 

Please install the patch attached with this answer record to resolve the issue in this release

Follow the instructions below to install the patches:

Extract the contents of the patches  to the desired patch directory location.

Set MYVIVADO environment variable to point to the 'vivado' directory inside the patches directory.

Linux:

setenv MYVIVADO <..>/ar_60072_pcie3_ultrascale_0_Rev_1_preliminary_patchrev1/vivado

Windows:

SET MYVIVADO=<..>/ar_60072_pcie3_ultrascale_0_Rev_1_preliminary_patchrev1/vivado

Run Vivado from the original location.

If the patch has been successfully applied, the Vivado version displayed in the output will be updated.


Revision History
04/16/2014 - Initial release

Attachments

Associated Attachments

AR# 60072
Date Created 04/02/2014
Last Updated 05/14/2014
Status Active
Type Known Issues
Devices
  • Virtex UltraScale
  • Kintex UltraScale
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)