UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60073

2014.1 Vivado Synthesis - ERROR: [Synth 8-3380] loop condition does not converge after 2000 iterations

Description

The following SystemVerilog code gives me an error in Vivado during Synthesis.
 
  ......
  str.limit = str.match == str.din ? 4-1 : 3-1;
  str.dout = 0;
   
 for(int i=0;i<=str.limit;i=i+1)
    begin
        if(str.din[i])
        begin
            str.dout[i] = 1;
            break;
        end
    end 

Vivado Synthesis is not able to calculate the loop limit value from the dynamic variable and displays the following error message.
      
ERROR: [Synth 8-3380] loop condition does not converge after 2000 iterations [top.sv:38]

Solution

Currently Vivado Synthesis does not support a loop limit that is determined by a dynamic variable.

This feature will be supported in a future release.
AR# 60073
Date Created 04/02/2014
Last Updated 04/16/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1