I wish to set a VHDL or Verilog module as Out-Of-Context (OOC), in a design which contains instantiation of IP cores which are already set in OOC mode.
Is this possible?
When I right click on the module file in the Vivado Hierarchy Panel in the sources view, the "Set as Out-Of-Context" option is grayed out.
This is a not a supported flow in Vivado Design Suite.
The file cannot be selected for OOC as it already contains an OOC IP core.
It is necessary to disable the IP as OOC and then regenerate the core.
This will enable you to choose "Set as Out-Of-Context" for the chosen module or file.
This feature is on the Roadmap and planned for a future release, however, the exact timeline is not yet known.
Note: In Vivado 2013.4 it was possible to select and set the upper level module as OOC but this led to errors in the implementation flow where the lower level IPs were black boxes.
This is again disabled in 2014.1.