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AR# 60076

Vivado IP Packager - Package IP with SystemVerilog Top Level


I have a piece of IP that is all SystemVerilog that I would like to package using IP Packager. 

When I try to package this, I get a critical warning stating that I cannot package with SystemVerilog as the top level file.

Is there any plan for Vivado to support this in the future?


In Vivado 2014.3 and earlier, SystemVerilog is supported but not as a top level file for IP Packager.
In Vivado 2014.4 a SystemVerilog file an be packaged as the top module as long as the structure of the ports and interfaces can be modeled as Verilog (Advanced SystemVerilog port structures are not supported). 
AR# 60076
Date 01/15/2015
Status Active
Type General Article
  • Vivado Design Suite - 2013.4
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