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AR# 60077

IBERT could fail timing in Artix-7

Description

Vivado 2013.4 - IBERT completes the Implementation with timing errors when the device is Artix-7 and the datarate is high.

For example IBERT with 6.25G lanes speed on Artix-7 xc7a200tffg1156-2.

Solution

This has been reported in Vivado 2013.4 and previous releases.

In particular, the default implementation completes with timing errors.


In this case trying a different implementation strategy will help.

Please follow the steps below in order to select a new strategy for the next implementation run.

1) In the design runs window, add a new implementation.

addimplementation.jpg
 
 


2)      Select "implementation" run.

chooseimpl.jpg
 
3) Choose a more efficient strategy.

newstrategy.jpg
 
 
4) In most of the cases the Performance_Explore or Performance_NetDelay_high strategies provide measurable improvements:
runs.jpg
 
 

AR# 60077
Date Created 04/02/2014
Last Updated 05/21/2014
Status Active
Type General Article
Devices
  • Artix-7
IP
  • ChipScope Pro IBERT for 7 Series GTP