We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60126

MIG 7 Series QDRII+ - Verify Pin Out fails to verify CK placement rule for QDRII+ SRAM designs


Version Found: 2.0 Rev 3
Version Resolved: See (Xilinx Answer 54025)

UG586 states that K/K# clocks must be kept in the same bank as the write data bank and that they should be placed on a DQSCCIO pin pair for QDRII+ SRAM designs. 

However, verifying the pin out in the MIG GUI fails to validate this rule.



To ensure that this rule is not violated users must manually verify this requirement. 

If this rule is violated the design may fail during implementation. 

Revision History
04/16/2014 - Initial Release
AR# 60126
Date Created 04/03/2014
Last Updated 07/01/2014
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • MIG 7 Series