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AR# 60139

7 Series FPGAs Transceiver Wizard v3.2 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.2 released with the Vivado 2014.1 design tool.

Solution

Known Issues and Release Notes

1. GTZ reset sequence

Issue:
The GTZ reset sequence produced by the wizard is not updated to the latest recommendation.

Work-around:
The recommended GTZ reset sequence in (Xilinx Answer 59038) should be implemented by the user.

 
2. Reference clock selection

Issue:
CPLLREFCLKSEL/PLL0REFCLKSEL/PLL1REFCLKSEL/QPLLREFCLKSEL is always set to 3b001( GTREFCLK0) even after selecting different reference clocks (for example GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1,GTGREFCLK)

Work-around:
Change the REFCLKSEL value to the appropriate value based on the selection below:
001: GTREFCLK0 selected
010: GTREFCLK1 selected
011: GTNORTHREFCLK0 selected
100: GTNORTHREFCLK1 selected
101: GTSOUTHREFCLK0 selected
110: GTSOUTHREFCLK1 selected
111: GTGREFCLK selected
 
3. Incorrect XDC constraints

Issue:
The constraints for the GT Wizard IP are incorrect which can cause issues with customer designs.

Work-around:
Please refer to (Xilinx Answer 60356).
 
4. Multiple RX reset issue in GTH and GTP

Issue:
All of the RX modules in the wizard for GTPE2 + GTHE2 execute a series of DRP operations (refer to (Xilinx Answer 53779) and (Xilinx Answer 53561)) that do the following:

(a) Read the DRP value.
(b) Write a DRP value (Force to 16-bit internal data width).
(c) Write the DRP value read in (a) to restore 20-bit internal data width.

If the module receives a reset after (b) but before (c) then on the next iteration it will read a 16-bit internal data width in step (a), and thus at the end of the sequence will restore a 16-bit internal data width.
This means that the GT is now permanently in 16-bit mode and the only way to recover is to reprogram the device.

Work-around:
Hold the original data width value in another register until all of the DRP operations all done.
If a reset is issued in between, restore the data width with the stored value. For more details, please refer to (Xilinx Answer 60489)
 
AR# 60139
Date Created 05/29/2015
Last Updated 06/16/2014
Status Active
Type Release Notes
Devices
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • More
  • Virtex-7
  • Virtex-7 HT
  • Less
Tools
  • Vivado Design Suite - 2014.1
IP
  • 7 Series FPGAs Transceivers Wizard