UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60181

MIG UltraScale DDR4/DDR3 - Timing violations may occur at higher data rates

Description

Version Found: v5.0
Version Resolved: See (Xilinx Answer 58435)

At the top supported data rates for each speed grade, timing violations may be seen within the MIG UltraScale DDR4/DDR3 cores. 

Solution

These timing violations are currently under analysis. 

Improvements will be made continually in the next two releases and will be resolved with the Vivado 2014.3 release.

Linked Answer Records

Master Answer Records

AR# 60181
Date Created 04/07/2014
Last Updated 09/23/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale