UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60181

UltraScale DDR4/DDR3 - Timing violations can occur at higher data rates

Description

Version Found: DDR4 v5.0, DDR3 v5.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, see (Xilinx Answer 69036) for DDR3

At the top supported data rates for each speed grade, timing violations might be seen within the MIG UltraScale DDR4/DDR3 cores.

Solution

These timing violations are currently under analysis.

Improvements will be made continually in the next two releases and will be resolved with the Vivado 2014.3 release.

Revision History:

04/16/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 60181
Date 02/02/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3
IP
  • MIG UltraScale
Page Bookmarked