UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60187

2014.1 System Generator - Waveform Viewer displays the incorrect clock period in multi-clock domain designs

Description

My design contains multiple clock islands which are running at different clock periods. 

I am experiencing some problems when viewing signals in the Waveform Viewer, it appears that the Clock signals are not being displayed correctly in certain scenarios.

1) If I monitor signal only from one clock domain within a multiple clock system, the clock signal name shown in the Waveform Viewer is not correct. The frequency of the clock displayed is correct but the name of the clock is not correct, hence it will traverse to the wrong clock domain when selected.

2) If you monitor output signals from the clock islands at the top level, the clock signal names and the frequency is not displayed correctly. 


Solution

This is a known issue in Vivado System Generator 2014.1 and will be resolved in 2014.2.

The data signals are correct, the issues are with the display of the clock signals for the multiple clock domains.


AR# 60187
Date Created 04/08/2014
Last Updated 04/17/2014
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.3