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AR# 6019

4.1i CORE Generator, MTI, Verilog - MTI reports "xxxx already exists" compilation errors when analyzing CORE Generator Verilog behavioral models

Description

Keywords: exist, Verilog, analyze, compile, ModelTech, MTI

Urgency: Standard

General Description:
When I compile the .v Verilog behavioral models extracted by get_models from the CORE Generator tree, error messages similar to the following are reported from MTI:

"C_REG_FD_V1_0 already exists"

Solution

Although these are flagged as errors, the messages are harmless and merely indicate that the same lower-level module is referenced by more than one higher-level macro in the CORE Generator Verilog behavioral simulation library. They do not mean that the models were not compiled properly.

If you wish to avoid these errors, you can compile the models using individual MTI "vlog" commands. The models should be compiled in the following order for the C_IP4 release:

async_fifo_v1_0.v
C_MEM_DP_BLOCK_V1_0.v
C_DIST_MEM_V1_0.v
C_COUNTER_BINARY_V1_0.v
C_COMPARE_V1_0.v
C_GATE_BIT_V1_0.v
C_TWOS_COMP_V1_0.v
C_SHIFT_RAM_V1_0.v
C_SHIFT_FD_V1_0.v
C_MUX_BUS_V1_0.v
C_MUX_BIT_V1_0.v
C_MUX_SLICE_BUFT_V1_0.v
C_MUX_SLICE_BUFE_V1_0.v
C_GATE_BUS_V1_0.v
C_GATE_BIT_BUS_V1_0.v
C_DECODE_BINARY_V1_0.v
PIPELINE.v
C_REG_LD_V1_0.v
C_ACCUM_V1_0.v
C_ADDSUB_V1_0.v
C_MEM_SP_BLOCK_V1_0.v
combfiltVHT.v
da_fir_v1_0.v
delayVHT.v
fifosyncVHT.v
integVHT.v
kcmpipeVHT.v
kcmVHT.v
kdcm_v1_0.v
syncramVHT.v
romrVHT.v
dpramVHT.v
MULT_VGEN_V1_0.v
C_REG_FD_V1_0.v
ncoiq_v1_0.v
nco_v1_0.v
pdafirVHT.v
sdafirVHT.v
DIVIDERVHT.v
trigtabl_v1_0.v
sqrootVHT.v
regceVHT.v
pscVHT.v
mux4VHT.v
mux3VHT.v
mux2VHT.v
adrleVHT.v
adreVHT.v
tsb32xVHT.v
tsb16xVHT.v
tsb16sVHT.v
subrleVHT.v
subreVHT.v
saddceVHT.v
cmpsVHT.v
addsVHT.v
acc2sVHT.v
mulVHT.v
AR# 6019
Date Created 03/25/1999
Last Updated 10/09/2003
Status Archive
Type General Article