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AR# 60193

2014.1 Vivado IP Flows - QuestaSim/Modelsim error received when simulating some IP cores which contain subcores (e.g. FIFO Generator)

Description

When running my simulation using QuestaSim/Modelsim, I receive the following error:

# ** Error: (vsim-13) Recompile proc_common_v4_0.sync_fifo_fg(implementation) because fifo_generator_v11_0.fifo_generator_v11_0 has changed.
# Load interrupted
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./board.do PAUSED at line 300

Why does this occur?

Is there any way to work around this?


Solution

This is a known issue and occurs because the FIFO Generator v11.0 is a subcore of the specific IP in your design and regardless of the language chosen for your project simulation both Verilog and VHDL simulation models are being delivered and included in the QuestaSim/Modelsim do-file.

vlog  -incr  -work fifo_generator_v11_0  "/path_to_project/project_1/axi_pcie_0_example/axi_pcie_0_example.srcs/sources_1/ip/axi_pcie_0/fifo_generator_v11_0/simulation/fifo_generator_v11_0.v"
vcom -work fifo_generator_v11_0 -93 "/path_to_project/project_1/axi_pcie_0_example/axi_pcie_0_example.srcs/sources_1/ip/axi_bram_ctrl_0/fifo_generator_v11_0/simulation/fifo_generator_v11_0.vhd"
With Vivado 2014.1 this can be avoided by setting the following parameter in the Tcl console prior to IP generation.
set_param ips.useProjectLanguageSubcoreFileDiscovery true

The issue will be fixed without parameter use in Vivado release 2014.2.


AR# 60193
Date Created 04/08/2014
Last Updated 05/20/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.1