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AR# 60204

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v14.2 - SGMII and 1588 - Updated XDC constraints needed to meet timing

Description

When using the Ethernet 1000BASE-X PCS/PMA or SGMII v14.2 IP with 1588 mode or SGMII with fabric elastic buffer, updates are needed to the XDC constraint to meet timing.

Note: 1588 mode is only selectable when using AXI Ethernet IPI core.

Solution

a) When using SGMII or 1588 timestamping with the fabric elastic buffer, change:
set_max_delay -from [get_cells -hier -filter {name =~ *transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[*]}] -to [get_pins -hier -filter { name =~ *reclock_rd_addrgray[*].sync_rd_addrgray/data_sync*/D}] 8 -datapath_only
set_max_delay -from [get_cells -hier -filter {name =~ *transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[*]}] -to [get_pins -hier -filter { name =~ *reclock_wr_addrgray[*].sync_wr_addrgray/data_sync*/D}] 16 -datapath_only
to:
set_max_delay -from [get_cells -hier -filter {name =~  *transceiver_inst/rx_elastic_buffer_inst/rd_addr_*_reg[*]}] -to [get_pins -hier -filter { name =~ *reclock_rd_addrgray[*].sync_rd_addrgray/data_sync*/D}] 8 -datapath_only
set_max_delay -from [get_cells -hier -filter {name =~ *transceiver_inst/rx_elastic_buffer_inst/wr_addr_*_reg[*]}] -to [get_pins -hier -filter { name =~ *reclock_wr_addrgray[*].sync_wr_addrgray/data_sync*/D}] 16 -datapath_only
b) When using 1588 mode, change the following constraint:
set_false_path -to [get_cells -hier -filter {name =~  *gpcs_pma_inst/INCLUDE_1588_common.RXRECRESET_PIPE_reg}]
to
set_false_path -to [get_cells -hier -filter {name =~  *gpcs_pma_inst/INCLUDE_1588_common.RXRECRESET_PIPE*reg}]
This is scheduled to be fixed in the next release of the core in Vivado 2014.2.

Linked Answer Records

Master Answer Records

AR# 60204
Date Created 04/08/2014
Last Updated 04/17/2014
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII