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AR# 60207

2014 Vivado - IP Flows Known Issues

Description

This answer record contains known issues for Vivado Design Suite 2014.x related to IP core flows, including IP customization, IP generation, IP Packager, IP Catalog and integration of IP cores in the Vivado design environment.

Solution

Outstanding Known IP Flow Issues in Vivado 2014.4

(Xilinx Answer 60195) - Editing a packaged IP in IP Packager and then discarding those edits may not completely remove all HDL file edits
(Xilinx Answer 60477) - Create peripheral in IP Packager gives Internal Exception error when creating AXI4 peripheral if default vendor is blank
(Xilinx Answer 63065) - Generating IP using Tcl commands creates  '_funcsim.vhdl/.v' files in incorrect language
(Xilinx Answer 63111) - Vivado will generate IP core stub file in root directory when project is on a mapped drive
(Xilinx Answer 63250) - The IP catalog may flickers and hangs if a project is pointing to an invalid IP repository
(Xilinx Answer 63564) - In non-project mode some VHDL IP cores are getting generated as Verilog
(Xilinx Answer 63865) - Interface IP ports list is missing from custom packaged IP
(Xilinx Answer 63916) - When creating a custom interface, the "Max Slaves" entry disappears if it is saved with a value of '0'

Known Issues Resolved in Vivado 2014.4

(Xilinx Answer 61962) - Spaces not allowed in path to .coe file
(Xilinx Answer 62291) - Block diagrams migrated from an older release have possible HDL file conflict - CRITICAL WARNING: [filemgmt 20-1741]
(Xilinx Answer 63064) - Delivery of encrypted source files merged into single file
 

Known Issues Resolved in Vivado 2014.3

(Xilinx Answer 59889) - IP Core example project cannot be opened using a UNC path
(Xilinx Answer 60191) - IP definitions get overwritten if an IP has the same name inside a subsystem package and outside it in the IP Integrator (IPI)
(Xilinx Answer 60337) - Cannot see my packaged IP in the IP Catalog or when searching in the IP Integrator block design?
(Xilinx Answer 60739) - Vivado IP Integrator forces upgrade to new version of custom IP when there are different versions
(Xilinx Answer 60975) - IP cores within a user IP result in implementation errors saying that the IP is a black box
(Xilinx Answer 61002) - A user IP GUI in IP Packager shows a parameter value set to '0' when parameter is derived by other parameters in Verilog code
(Xilinx Answer 61043) - IP Integrator design fails to upgrade - ERROR: [Coretcl 2-1043] upgrade_ip failed for 'k7bb1k' A current version of the IP 'xilinx.com:ip:axi_10g_ethernet:1.2'
(Xilinx Answer 61044) - Tcl upgrade can lead to: Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) when closing project
(Xilinx Answer 61045) - Using upgrade_ip results in: boost: mutex lock failed in pthread_mutex_lock: Invalid argument
(Xilinx Answer 61807) - IP packager does not indicate when project files have changed
(Xilinx Answer 61121) - Ability to "Disable/Enable"' the xdc file of an IP core using the right-click menu is not available
(Xilinx Answer 61181) - Selecting "Create HDL Wrapper" for a block design gives "bad lexical cast: source type value could not be interpreted as target"
(Xilinx Answer 61647) - After modifying a top level port name in the source code, the port name in the IP Packager window does not updated
(Xilinx Answer 62234) - Vivado hierarchy display incorrectly shows an IP under the block diagram as locked after READ-ONLY permission is changed

Known Issues Resolved in Vivado 2014.2

(Xilinx Answer 60193) - QuestaSim/ModelSim error out when simulating some IP cores which contain subcores (e.g. FIFO Generator)
(Xilinx Answer 60271) - IP Packager GUI does not consider user specified Archive name during "Review and Package" step
(Xilinx Answer 60477) - Create peripheral in IP Packager gives Internal Exception error when creating AXI4 peripheral
(Xilinx Answer 60531) - Erroneous LOCK_PINS error for example design of GTZ generated in 7 Series FPGAs Transceivers Wizard 
(Xilinx Answer 63855) - A newly added bus parameter is not displayed in the Parameters Table in the Edit IP Bus Interface window in IP Packager

Known Issues Resolved in Vivado 2014.1

(Xilinx Answer 57882) - Create, Import Peripheral Wizard generated IP is missing the Support Narrow Burst parameter on the AXI4 Master Interface
(Xilinx Answer 58445) - "ERROR: [Vivado 12-563] The file type 'IP-XACT' is not user settable"
(Xilinx Answer 58779) - Compile Order tab (GUI) does not show constraint files in an OOC Block Design
(Xilinx Answer 58939) - After modifying the IP configuration in IP Packager, the "Refresh" option is missing in the "IP GUI Customization Layout"
(Xilinx Answer 59575) - Open Example Design for GTZ core fails when both octals are used.


AR# 60207
Date Created 04/08/2014
Last Updated 03/19/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.1