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AR# 60208

2014 Vivado - Vivado User Interface (GUI) and Project Management Known Issues


This answer record contains a list of Vivado Design Suite graphical user interface and project management known issues for Vivado IDE 2014.x.


Outstanding Known Issues in Vivado Design Suite 2014.4

(Xilinx Answer 53243) - "Replace File" directory browser does not update "Date Modified" field
(Xilinx Answer 55052) - Vivado does not preserve XDC wildcards in generated Design Check Point (DCP)
(Xilinx Answer 55418) - Message suppression rules are not editable
(Xilinx Answer 58937) - Simulating IP core generated files gives: ERROR: [XSIM 43-3225] Can not find design unit work.<IP core TB> in library work located at xsim.dir/work
(Xilinx Answer 60242) - calibration.elf is not used in behavioral simulation for MIG UltraScale example design 
(Xilinx Answer 62708) - ASYNC_REG property is not showing in the Property window 
(Xilinx Answer 62768) - Generated 3rd party simulator scripts created with the wrong library for simulation testbench files if they are assigned to a different library than the design VHDL files
(Xilinx Answer 62834) - LUT equation box displays incorrect value when the LUT4's INIT value is 16'hABFB
(Xilinx Answer 62889) - Vivado IDE Error "Abnormal program termination (11)" when OBUFDS that has a LOC constraint set but no IOSTANDARD
(Xilinx Answer 63180) - Selecting "Place ports in an Area" and then clicking on the Floorplanner will cause an Internal Exception
(Xilinx Answer 63347) - Vivado gives Abnormal program termination while opening an EDIF netlist created with newer versions of Synopsys Synplify / Pro
(Xilinx Answer 63662) - User Created DRC fails to be reported as proper severity

Known Issues Resolved in Vivado 2014.4

(Xilinx Answer 63875) - "Edit Device Properties" entries silently take invalid value

Known Issues Resolved in Vivado 2014.3

(Xilinx Answer 55444) - Data2mem fails if the path to the BMM file contains a directory named microblaze"
(Xilinx Answer 59277) - Grouped messages in the "Message" console only show the process-message ID (Not the message)
(Xilinx Answer 59420) - Export_hardware in non-project mode results in "No open project. Please use Save Project As ..." error
(Xilinx Answer 59871) - Pixel left in Schematic Viewer after Pop Up window
(Xilinx Answer 60340) - MULT18X18S instantiated in my design but when retargeted in Vivado it appears to be incorrect
(Xilinx Answer 60514) - After changing the target simulator in Tcl console, the target simulator shown in Vivado IDE does not change
(Xilinx Answer 60772) - Language template comments for IDELAYE3 of Kintex/Virtex UltraScale device are incorrect
(Xilinx Answer 60948) - Synthesis runs on all block designs (BD) that are defined as OOC, including those not currently used in the project
(Xilinx Answer 60981) - Tcl App Store: New app/company name not visible unless the catalog XML is updated
(Xilinx Answer 61033) - ERROR: [Common 17-53] User Exception: Constraints cannot be saved due to read-only file:<>/<xxxx>.xdc
(Xilinx Answer 61037) - Archive project and Copy Runs do not bring in tcl.pre and tcl.post script files
(Xilinx Answer 61145) - Project created from write_project_tcl will have IP OOC runs status set to "Not started" even when the original project had IP output products generated
(Xilinx Answer 61297) - Null pointer Exception when moving block text in column selection mode
(Xilinx Answer 61446) - When I open a synthesized design I get: "ERROR: [Common 17-48] File not found: .../my_proj.data/ddr2_IP/ports.xml" 
(Xilinx Answer 61451) - Error issued when opening the synthesized/implemented design with only one .xpr file
(Xilinx Answer 62225) - Tcl command export_simulation gives: ERROR: [Vivado-projutils-9] The specified object could not be found in the project:<project name>
(Xilinx Answer 62226) - Opening a Vivado project gives CRITICAL WARNING: [Project 1-124] XILINX environment variable undefined
(Xilinx Answer 62229) - After upgrading my Vivado project to version 2014.2, Generate Block Design fails to execute
(Xilinx Answer 62302) - Vivado give Unexpected error has occurred with "librdi_common.so if the device field of a project file is Null
(Xilinx Answer 62786) - designprops.xml is missing after constraint (mark debug) modification
(Xilinx Answer 63322) - Message view gets "out of Sync" give "ERROR: [Vivado 12-106] *** Exception: java.lang.ArrayIndexOutOfBoundsException: 3 >= 3

Known Issues Resolved in Vivado 2014.2

(Xilinx Answer 53011) - There is a delay in the output to the "Log" tab in the "Properties" window in comparison with the main "Log" pane
(Xilinx Answer 58504) - JAVA Runtime Environment (JRE) is not picked up using MYVIVADO environment variable
(Xilinx Answer 59875) - Running a command from the Tclstore in Vivado 2014.1 results in: invalid command name "<proc name>"
(Xilinx Answer 60121) - No warning is issues to indicate that Vivado does not support direct instantiation of modules from the "XilinxCoreLib" library
(Xilinx Answer 60184) - Java HotSpot(TM) Server VM warning when running 32-bit vivado on a 64-bit Linux platform
(Xilinx Answer 60186) - Project Archive does not include the runs directory when runs are in progress
(Xilinx Answer 60206) - Removing ELF File after Implementation still populates the bitstream with the removed ELF File contents
(Xilinx Answer 60209) - GUI does not show one of the two associations of an ELF file under both Design and Simulation Sources in a Dual MicroBlaze IPI Design
(Xilinx Answer 60243) - The Associate Elf File Dialog doesn't have a way to deselect all files
(Xilinx Answer 60244) - Two instances of the same ELF file show up in Simulation sources
(Xilinx Answer 60246) - Synthesis and Implementation go out-of-date during ELF file Association 
(Xilinx Answer 60248) - When elf file is added as a design source and a simulation source, a warning indicates that the 'xxx.elf' cannot be added to the project ...
(Xilinx Answer 60270) - SCOPED_TO_CELLS constraint applied to cells using wildcard (*) is only applied to 1st cell found 
(Xilinx Answer 60283) - tclstore does not properly get git's http.proxy global variable on Windows
(Xilinx Answer 60400) - Write_project_tcl - bad index "4294967296": must be integer?[+-]integer? or end?[+-]integer?
(Xilinx Answer 60401) - write_project_tcl does not work in 2014.1 resulting in ERROR: [Common 17-58] '' is not a valid first class Tcl object
(Xilinx Answer 60463) - Exception after sorting Name column in Connectivity tab
(Xilinx Answer 60987) - "undo" does not work for commands between "startgroup" and "endgroup"
(Xilinx Answer 61051) - Tcl App Store: Catalog refresh fails on Windows but no warning/error is issued
(Xilinx Answer 61135) - report_utilization lists number of LUTs and Registers with incorrect decimal point format
(Xilinx Answer 61140) - The read_checkpoint -netlist_only switch is ignored without indicating the switch has been deprecated
(Xilinx Answer 61147) - Report DRC GUI creates incorrect command when checking only user-defined DRC's
(Xilinx Answer 62227) - Vivado must be restarted after refreshing the Tcl AppStore in order to use all procedures
(Xilinx Answer 63856) - Bitstream options are not updated for second project opened in a single Vivado session

Known Issues Resolved in Vivado 2014.1

(Xilinx Answer 57653) - A Board Design (BD) file shows up in the Hierarchy view even when it is not found
(Xilinx Answer 57776) - Compile order of constraints ignored in write_project_tcl
(Xilinx Answer 57878) - Part Compatibility settings are not updated if the project part is changed
(Xilinx Answer 57935) - Write_project_tcl led to "ERROR: [Common 17-170] Unknown option '-mode out_of_context', please type 'set_property -help' for usage info."
(Xilinx Answer 58535) - VHDL parser could crash if special accents are used in the port definition
(Xilinx Answer 58445) - "ERROR: [Vivado 12-563] The file type 'IP-XACT' is not user settable"
(Xilinx Answer 58679) - Pop-up information about confirming status of the compiled libraries command is incorrect
(Xilinx Answer 59045) - XDC file is overwritten instead of append when saving constraints in Implemented design
(Xilinx Answer 59054) - Auto completion does not include "write_inferred_xdc" in the completion list when you type "write_"
(Xilinx Answer 59108) - Changing a Device Property value to a blank field results in an incorrect Tcl command
(Xilinx Answer 59239) - write_project_tcl generated Tcl script contains an absolute path and improperly handles user IP and unmanaged Tcl files
(Xilinx Answer 59520) - Exec command is not fully supported on Windows platform
(Xilinx Answer 59950) - Can not select Edit Device Properties from the drop down menu for a Zynq design
(Xilinx Answer 60016) - Running read_checkpoint on synthesized DCP opens the implemented design instead of checkpoint design
(Xilinx Answer 60017) - The Find command returns multiple net segments instead of the top net of hierarchical group
(Xilinx Answer 60932) - Internal Error issued when modifying the color value of Windows' background without opening a project
(Xilinx Answer 60939) - Vivado reports incorrect success message if synthesis fails because of non-availability of license
(Xilinx Answer 61132) - Vivado Tcl package version is not compatible with the release version

AR# 60208
Date 03/31/2015
Status Archive
Type Known Issues
  • Vivado Design Suite - 2014.1
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