We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 60258: Artix-7 GTP - reference clock routing to adjacent QUADs fails in placement
Artix-7 GTP - reference clock routing to adjacent QUADs fails in placement
When manually routing a reference clock from an adjacent quad the following errors are received:
[Place 30-512] Clock region assignment has failed. Clock buffer 'gtwizard_0_support_i/gt_usrclk_source/ibufds_instq1_clk0' (IBUFDS_GTE2) is placed at site IBUFDS_GTE2_X1Y0 in CLOCKREGION_X1Y0. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X1Y0 and CLOCKREGION_X1Y0. One of its loads 'gtwizard_0_support_i/common0_i/gtpe2_common_i' (GTPE2_COMMON) is placed in site GTPE2_COMMON_X0Y0 in CLOCKREGION_X0Y0 which is outside the permissible area.
The software is incorrectly using fabric clock regions on the GTP reference clock routing.
This is a known issue, which is resolved in the 2014.2 release.