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AR# 60295

High Speed SelectIO Wizard v1.0 Beta- Vivado 2014.1 Release Notes & Known Issues

Description

This Release Note is for the High Speed SelectIO Wizard v1.0 released in Vivado 2014.1 and contains the following information:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues

Solution

General Information

The High Speed SelectIO Wizard v1.0 supports the Xilinx UltraScale FPGAs. 

The High Speed SelectIO Wizard created a HDL file (Verilog) that contains I/O and clocking logic such as RX/TX_BITSLICE_CONTROL and PLLE3 blocks customized to the users interface requirements. 

Pin LOC update in this wizard updates the RTL to provide required connectivity among blocks.

V1.0 is the initial release of this wizard.

New Features in v1.0

Initial Release

Bug Fixes in v1.0

None

Known Issues in v1.0

Issue 1:
High Speed SelectIO Wizard v1.0 core in 2014.1 will fail in simulation for clk_src = EXTERNAL when data width other than 1 is selected. This is a simulation model issue.
Workaround: Switch to clk_src = PLL

Issue 2:
High Speed SelectIO Wizard v1.0 core in 2014.1 will not work when RX DELAY CASCADE is true. This is a simulation model issue.
Workaround: No workaround. Users cannot use this feature.

Issue 3:
High Speed SelectIO Wizard v1.0 core in 2014.1 will have a TIMING=17 Warning. This may impact the performance on Hardware.
Workaround: No workaround.

Revision History
15/04/14 - Initial Release


AR# 60295
Date Created 04/15/2014
Last Updated 05/22/2014
Status Active
Type Release Notes
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1