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AR# 60307

Aurora 64B66B v9.2 - Errors while launching post synthesis or post implementation functional simulation for Simplex cores


In Aurora 64B66B v9.2 core, when simplex configuration is chosen, post synthesis or post implementation Functional simulation fails with the following errors.

Error: (vopt-2732) Module parameter 'GTHE3_COMMON_BGBYPASSB_TIE_EN' not found for override at ./my_ip_example/my_ip_example.srcs/sources_1/ip/tx_my_ip/tx_my_ip/example_design/tx_my_ip_gt_gthe3_common_wrapper.v(309).


Error: (vopt-7) Failed to open info file "xil_defaultlib/_info" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: ./my_ip_example/my_ip_example.srcs/sources_1/ip/rx_my_ip/rx_my_ip/example_design/rx_my_ip_gt_gthe3_common_wrapper.v(309): Module 'gtwizard_ultrascale_v1_2_gthe3_common' is not defined.

These errors appear in cases where the core is generated with the dataflow_config options chosen as either TX-Simplex or RX-Simplex and using "Shared logic in core" (or) "Shared logic in example design" options.

This answer record provides guidelines on how to launch post implementation functional simulation successfully.


Please follow the steps below to resolve these errors.

  1. Create a simplex TX core with support logic in core from Aurora 64b66b v9.2 core from 2014.1.

  2. Open the example design.

  3. Before running post synthesis or post implementation simulation, run the tcl command below in the Vivado tcl console for the example design:
    add_files -scan_for_includes -fileset [current_fileset -simset] [list [file join ./<USER_COMPONENT_NAME>_example.srcs/sources_1/ip/RX_<USER_COMPONENT_NAME>/RX_<USER_COMPONENT_NAME>/example_design/gtwizard_ultrascale_v1_2_gthe3_common.v]]

  4. Replace the module definition "gtwizard_ultrascale_v1_2_gthe3_common" with "RX_ gtwizard_ultrascale_v1_2_gthe3_common" in the following files:

    • gtwizard_ultrascale_v1_2_gthe3_common.v

    • RX_<USER_COMPONENT_NAME>_gt_gthe3_common_wrapper.v

    The above files are present in ./<USER_COMPONENT_NAME>_example.srcs/sources_1/ip/RX_<USER_COMPONENT_NAME>/RX_<USER_COMPONENT_NAME>/example_design

  5. Run the simulation.


  • All of the above steps are required if you have selected the "Shared logic in core" option.

  • Step 1, 2 & 4 only are required if you have selected the "Shared logic in example design" option.

  • These Steps were listed for TX-Simplex based cores, for RX-Simplex based cores, replace the prefix RX_ with TX_.

Revision History:

04/16/2014 - Initial Release

AR# 60307
Date 05/21/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2014.1
  • Aurora 64B/66B
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