We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60333

ISE14.7 - Spartan-6 GTP Wizard v1.11 Selects PLL0 instead of PLL1 when only GTP1 is selected


GTP wrapper files generated by selecting GTP1 in the ISE14.7 Spartan-6 GTP Wizard v1.11 do not work in simulation or hardware.

The PLL lock indicator PLLLKDET1 does not get asserted.



This issue occurs because the Wizard is selecting PLL0 instead of PLL1 in the generated example design. 

PLL0 is in power down state which results in PLLLKDET1 not getting asserted.

In the s6_gtp_tx_v1_11_tile0gtp1.v module, you will need to set the TILE_PLL_SOURCE_0 & TILE_PLL_SOURCE_1 to PLL0.

TILE_PLL_SOURCE_1 should be set to PLL1.

Changing the following lines resolves this issue:

Before change: (Line 192,193)


After change: (Line 192,193)



Revision History:

12/10/2014 - Initial Release

AR# 60333
Date Created 04/17/2014
Last Updated 01/26/2015
Status Active
Type General Article
  • Spartan-6
  • ISE Design Suite - 14.7
  • Spartan-6 FPGA GTP Transceiver Wizard