I have a design from ISE 13.x or earlier which contains HDL code instantiating a MULT18X18S primitive.
If I import this code into Vivado, This multiplier is retargeted correctly to a DSP48E1 primitive.
However, the MREG attribute of this DSP48E1 is set to "0" incorrectly, this should be "1".
This issue will be fixed in the Vivado 2014.3 release.
There are two workarounds available for earlier releases: