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AR# 60349

2014.1 Vivado Timing - report_timing reports BELs and Components to have zero delays after changing the speed grade


I am attempting to analyze a design by changing the speed grade of the design.

However report_timing shows Basic Elements of Logic (BEL)'s and Components to have zero delays.

Is this a known issue?


This is a known issue and is scheduled to be fixed in a future release. 

The current work-around isto use the following "-recalculate_delays" option of report_timing:

open_checkpoint *dcp 
set_speed_grade -1 
report_timing -recalculate_delays 
AR# 60349
Date 08/22/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2014.1
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