We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60367

Vivado 2014.1: using ap_shift_reg with a struct that contain a struct does not complete with csynth_design


This issue occurs when using "ap_shift_reg" with a struct that contains another struct and where at least 2 members of the inner struct are read from a shift register using read() of ap_shift_reg.

The tool becomes stuck after the point below:

@I [HLS-10] Checking synthesizability ...

As well as after any other directives that have been applied.


The issue is that the read method is called several times.

For example: 

(the structs definitions are shown at the bottom of this AR) 

  static ap_shift_reg shiftreg;
/// ... more code ...
  mysum += shiftreg.read(i).inner.Re;
  mysum -= shiftreg.read(i).inner.Im;

A workaround is to recode it to use an intermediate variable holding the read value:

  data_struct tmp = shiftreg.read(i);
  mysum += tmp.inner.Re;
  mysum -= tmp.inner.Im;

Please note that "ap_shift_reg" will map directly to SRL resources in the FPGA.

If normal registers need to be used, the user will need to code a shift register explicitly.


The example attached gives a worked example - this is just an example to illustrate the issue with version 2014.1 of the tool.

This issue will be addressed in a future release of Vivado HLS.

Struct definitions in the above example:

struct inner_struct {
    float Re;
    float Im;

struct data_struct {
    bool condition;
    inner_struct inner;


Associated Attachments

Name File Size File Type
AR60367_ap_shift_reg.zip 1 KB ZIP
AR# 60367
Date Created 04/22/2014
Last Updated 06/19/2014
Status Active
Type Known Issues
  • Vivado Design Suite
  • Vivado Design Suite - 2014.1