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AR# 60440

AXI Bridge for PCI Express v2.3 (Rev1) - Core incorrectly decodes AXI BAR addresses


Version Found: v2.3 (Rev1)
Version Resolved and other Known Issues: See
(Xilinx Answer 54646)

This issue arises when a packet is generated at the AXI Slave interface of the AXI Bridge for PCI Express v2.3 (Rev1) core, (for example an outgoing PCIe Memory Write/Read packet).

The core may incorrectly decode AXI BAR addresses which will result in hitting another AXI BAR or missing it entirely.


This is a known issue which is due to be fixed in a future release of the core. 

To work around this issue, replace the following files with the files attached to this answer record.

  • axi_slave_read.vhd
  • axi_slave_write.vhd 

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
07/08/2014 - Initial Release


Associated Attachments

Name File Size File Type
axi_slave_read.vhd 49 KB VHD
axi_slave_write.vhd 45 KB VHD
AR# 60440
Date Created 04/28/2014
Last Updated 08/12/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.1
  • AXI PCI Express (PCIe)