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AR# 60454

Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier

Description

There is no initialization of the DDR IOB registers 0XF8000B58-B6C which will result in drive strength and slew rate settings on the PS DDR I/O pins that are different than intended and characterized. 

All Zynq-7000 PS DDR3/DDR3L/DDR2/LPDDR2 users are encouraged to incorporate the following fixes for increased margin and stability.

Solution

Vivado 2013.3 and earlier:

A Vivado 2014.1 or later ps7_init.tcl or ps7_init.c may be substituted.

If upgrading the entire user project is not feasible, a 2014.1 or later block diagram with only a Processing System 7 IP instance with the same IP configuration settings may be used as a donor project.

To generate the ps7_init.c and ps7_init.tcl files:

Generate the Block Design (solving any minor design rule errors as necessary), Click File-> Export Hardware for SDK, and then launch SDK.

EDK/XPS:

A patch for ISE/EDK 14.7 is available:

ISE/EDK  Patch Details:

The attached patch file addresses the following issues in EDK XPS 14.7 for Zynq-7000 devices:

- (This issue) DDR IO's are not properly configured (CR:794357)
(Xilinx Answer 60454)


- PS DDRC LPDDR2 Controller Instability (CR:782178)
(Xilinx Answer 59963)

- Other changes may also exist in the resulting ps7_init.tcl or ps7_init.c.

Consider reviewing the differences between the ps7_init.c and
ps7_init.tcl.
 
ISE/EDK Patch  Installation/Use:

Install the Patch by extracting the contents of the ".zip" archive to the root directory of the ISE install directory (example: C:\Xilinx\14.7\ISE_DS\ISE) .

Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.
 
Note: You might need a system administrator to install the Patch if you do not have write permissions to the Xilinx install directory.

Resolution

This issue has been fixed in Vivado release 2013.4 and later.

Attachments

Associated Attachments

Name File Size File Type
ar60454_edk_14_7_preliminary_rev1.zip 1 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47915 Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices N/A N/A
AR# 60454
Date Created 04/29/2014
Last Updated 05/30/2014
Status Active
Type Design Advisory
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q
Tools
  • EDK - 14.7
  • EDK - 14.6
  • EDK - 14.5
  • More
  • EDK - 14.4
  • EDK - 14.3
  • EDK - 14.2
  • EDK - 14.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2012.4
  • Less