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AR# 60488

7 Series FPGA Transceivers Wizard v3.0: GTX/GTH/GTP reset sequence might not complete successfully with the reset FSM's from the wizard


When using the GTX/GTH/GTP reset Finite State Machines (FSM's) from the 7 Series FPGA Transceivers Wizard v3.0, it can happen that the TX and RX reset sequence does not complete successfully.

If this occurs, TX/RXRESETDONE is not asserted successfully and Q/CPLLLOCK continues to toggle because the FSM executes reset continuously.


The workaround for this issue is to update the logic in the TX/RX startup FSM's ("gtwizard_*_tx/rx_startup_fsm.v/vhd") as below:

Replace this text:

if (time_tlock_max = '1' and mmcm_lock_reclocked = '0')


if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0')

Note: In general it is better to add a condition to check for reset_time_out = 0 whenever a time_out is checked in the start up FSM's.

This has been fixed in version 3.0 or later of the Wizard which is included in Vivado 2013.3 or later.

AR# 60488
Date Created 05/01/2014
Last Updated 05/21/2014
Status Active
Type General Article
  • 7 Series FPGAs Transceivers Wizard